EEL 510389 – Digital Systems and Reconfigurable Devices
Graduate Program in Electrical Engineering
Course code: EEL 510389
Course name: Digital Systems and Reconfigurable Devices
Course name (in Portuguese): Sistemas Digitais e Dispositivos Lógicos Reconfiguráveis
Credits: 4
Professor: Eduardo Augusto Bezerra
Term: 2021/1 - Thursday 17:10-18:00-18:50-19:40-20:30
Google meet: https://meet.google.com/okn-prsq-euu
Syllabus
Introduction to digital systems; Combinational and sequential circuits; Digital systems design at the register transfer level (RTL); CPU classical model with datapath and control unit; Reconfigurable devices; Digital systems prototyping.
Ementa
Conceitos introdutórios de sistemas digitais; Circuitos combinacionais e sequenciais; Projeto de sistemas digitais no nível de transferência entre registradores (RT); Modelo clássico de CPU com bloco de dados e bloco de controle; Dispositivos lógicos reconfiguráveis; Prototipação de sistemas digitais.
Methodology
- The contents will be introduced through lectures with the aid of multimedia resources.
- Laboratory sessions where the students follow tutorials provided by the lecturer with instructions for using tools and development boards.
- Reading and discussion of classical and state-of-the-art scientific papers.
- Presentation of seminars prepared by the students.
- The supporting texts and source codes used in the lectures and in the laboratory sessions are available on the course’s page and on the Moodle platform.
- Hardware Description Languages (HDLs) will be used throughout the course to describe the circuits and digital systems presented.
Synopsis
- Introduction
- Combinational circuits
- Sequential circuits
- Reconfigurable logics
- The design flow of digital systems using EDA tools
- Digital systems and hardware description languages
- Boolean Algebra and Boolean Expressions
- Encoders, Decoders, Multiplexers, Demultiplexers
- Arithmetic circuits, adders, comparators, counters, shifters, multipliers
- Arithmetic and Logic Unit (ALU): synthesis and simulation with a hardware description language
- Sequential circuits and controllers
- Latches and flip-flops
- Finite State Machines (FSMs)
- Controllers design using FSMs
- FSMs synthesis using a hardware description language
- Case study
- Datapath and control unit design for a processing unit
- Register Transfer Level (RTL) description of a processing unit using a hardware description language
- Simulation, logical synthesis, physical synthesis, and hardware prototyping of a processing unit
Student assessment
- The final grade (FT) is calculated through the geometric mean: FT = sqrt(P x S), where P is the end-of-term project grade, and S is the grade for the preparation/presentation of the seminars.
- Pass conditions: class attendance > 75% and FT >= 7,0
Reading list
- David A. Patterson, John L. Hennessy, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, Morgan Kaufmann, 2017.
- Frank Vahid, “Digital Design”, 1st ed., Wiley, 2007.
- Eduardo Bezerra and Djones Lettnin, “Synthesizable VHDL Design for FPGAs“, Springer, 2014.
- Randy Katz, Gaetano Borrielo, “Contemporary Logic Design””, 2nd ed., Prentice Hall, 2005.
- John F. Wakerly, “Digital design: Principles and practices”, Prentice Hall, 2005.
- Volnei A. Pedroni, “Circuit Design with VHDL”, The MIT Press, 2004.
- Frank Vahid, “VHDL for Digital Design”, 1st ed., Wiley, 2007.
- Pong P. Chu, “FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version”, Wiley-Interscience, 2008.
Supporting tools
- Frank Vahid’s slides: author page and local copy
- Frank Vahid’s exercises: exercises
- Web tools: https://www.edaplayground.com/
- DE1-SOC documentation and tools:
- Development kit pinout – Pinos.csv
- Lab. 1 EEL5105 – Introduction to Quartus II
- Lab. 2 EEL5105 – Quartus II and ModelSim
- VHDL:
End-of-term project
Schedule
Lecture | Contents | ||||||||||||||||||||||||
1 | Digital systems and VHDL synthesis for FPGAs:
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2 | Digital systems and VHDL synthesis for FPGAs: | ||||||||||||||||||||||||
3 | Digital systems testing and VHDL Test Benches:
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4 | Sequential circuits and FSMs:
Supporting papers:
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5 |
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6 | RISC-V case study
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7 | RISC-V case study
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8 | RISC-V case study
Exercises
Tools
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9 | RISC-V case study
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10 | End-of-term project definition – Discussion on the expected architecture for the end-of-term project (memories, I/O, datapath, control unit). | ||||||||||||||||||||||||
11 |
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12 | End-of-term project (10%): Technical report – preliminary. The block diagrams used in the text must be prepared by the students. Slides/book copies will not be considered! | ||||||||||||||||||||||||
13 | End-of-term project (10%): VHDL + testbench of the datapath. | ||||||||||||||||||||||||
14 | End-of-term project (10%): VHDL + testbench of the control unit. | ||||||||||||||||||||||||
15 | End-of-term project (20%): VHDL + testbench of the datapath and control unit integration. | ||||||||||||||||||||||||
16 | End-of-term project (50%): Demonstration of the proposed RISC-V implementation in a simulator, and final report upload in the Moodle platform. |
2021/1 Seminars schedule:
- 15/Jul. [10%] Seminars – Research papers
- 22/Jul. [20%] Seminars – RISC-V
- 05/Aug. [40%] Seminars – RISC-V
- 12/Aug. [30%] Seminars – RISC-V
2021/1 End-or-term project deliveries:
- 02/Sept. [10%] Technical report – preliminary. The block diagrams used in the text must be prepared by the students. Slides/book copies will not be considered!
- 09/Sept. [10%] VHDL + testbench of the datapath.
- 16/Sept. [10%] VHDL + testbench of the control unit.
- 23/Sept. [20%] VHDL + testbench of the datapath and control unit integration.
- 30/Sept. [50%] Demonstration of the proposed RISC-V implementation in a simulator, and final report upload in the Moodle platform.
Papers presented in past editions (last update in 2021):
- “FPGA Implementation of Floating Point Based Cuckoo Search Algorithm“, IEEE Access, 2019.
- “Validation Techniques for Fault Emulation of SRAM-based FPGAs“, IEEE Transactions on Nuclear Science, 2015.
- “RV-CNN: Flexible and Efficient Instruction Set for CNNs Based on RISC-V Processors“, APPT – Advanced Parallel Processing Technologies, 2019.
- “A New Automatic Real-Time Crop Row Recognition Based on SoC-FPGA“, IEEE Access, 2020.
- “Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA“, IEEE Access, 2020.
- “Design of a High Accuracy and Real-Time Indoor Positioning System Based on Coding Point Identification and its FPGA Implementation“, 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2020.
- “Design and Implementation of Real-Time Localization Algorithms Based on FPGA for Positioning and Tracking“, IEEE Eurasia Conference on IOT, Communication and Engineering (ECICE), 2019
- “FPGA Implementation of a Synchronization Circuit for Arbitrary Trigger Sequences“, IEEE Transactions on Instrumentation and Measurement, 2020.
- “FPGA-Based System for In-Line Measurement of Velocity Profiles of Fluids in Industrial Pipe Flow“, IEEE Transactions on Industrial Electronics, 2016.
- “The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology“, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019.
- “Fiber-Fed Distributed Antenna System in an FPGA Software Defined Radio for 5G Demonstration“, IEEE Transactions on Circuits and Systems II, 2020.
- “APSoC Architecture Design of 2.4 GHz ZigBee Baseband Transceiver for IoT Application“, International Conference on Radar, Antenna, Microwave, Electronics, and Telecommunications (ICRAMET), 2019.
- “An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs“, IEEE Transactions on Computers, 2019.
- “Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs“, IEEE Transactions on Computers, 2018.
- “Real-Time FPGA-Based Hardware Neural Network for Fault Detection and Isolation in More Electric Aircraft“, IEEE Acess, 2019.
- “A Fast and Efficient Fault Tree Analysis Using Approximate Computing“, 15th European Dependable Computing Conference (EDCC), 2019.
- “VHDL Based Circuits Design and Synthesis on FPGA: A Dice Game Examplefor Education“, IEEE 2nd International Conference on Signal and Image Processing (ICSIP), 2017.
- “Deadlock detection in FPGA design: A practical approach“, Tsinghua Science and Technology, 2015.
- “Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects“, IEEE Acess, 2018.
- Hung, E.; Quinton, B.; Wilton, S.J.E., “Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics,” IEEE Design & Test, vol.30, no.4, pp.8,15, Aug. 2013.
- Subramanyan, P.; Tsiskaridze, N.; Wenchao Li; Gascon, A.; Wei Yang Tan; Tiwari, A.; Shankar, N.; Seshia, S.A.; Malik, S., “Reverse Engineering Digital Circuits Using Structural and Functional Analyses,” IEEE Transactions on Emerging Topics in Computing, vol.2, no.1, pp.63,80, March 2014
- Azcondo, F.J.; de Castro, A.; Brañas, C., “Course on Digital Electronics Oriented to Describing Systems in VHDL,” IEEE Transactions on Industrial Electronics, vol.57, no.10, pp.3308,3316, Oct. 2010.
- Abdallah, A.; Feron, E.M.; Hellestrand, G.; Koopman, P.; Wolf, M., “Hardware/Software Codesign of Aerospace and Automotive Systems,” Proceedings of the IEEE, vol.98, no.4, pp.584,602, April 2010.
- Brackenbury, L.E.M.; Plana, L.A.; Pepper, J., “System-on-Chip Design and Implementation,” IEEE Transactions on Education, vol.53, no.2, pp.272,281, May 2010.
- Guralnik, E.; Aharoni, M.; Birnbaum, A.J.; Koyfman, A., “Simulation-Based Verification of Floating-Point Division,” IEEE Transactions on Computers, vol.60, no.2, pp.176,188, Feb. 2011.
- “FPGA architectural research: a survey“; Brown, S.; IEEE Design & Test of Computers; Vol 13; issue 4; pp. 9; 1996.
- “Convergence in reconfigurable embedded systems“; Valderrama, Carlos Jojczyk, Laurent Possa, Paulo; IEEE ICECS 2010; pp. 1144; 12-15 Dec. 2010.
- “Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs“; S.Z. Ahmed et. al.; FPL 2010; Aug. 31 2010-Sept 2 2010.
- “Closing the SoC design gap“; Henkel, J.; Computer; Vol 36; issue 9; pp. 119-121; Sept. 2003.
- “A CubeSat design to validate the Virtex-5 FPGA for spaceborne image processing“; D. L. Bekker et. al.; IEEE Aerospace Conference; pp. 1; Mar. 2010.
- “Architecture of field-programmable gate arrays“; Rose, J. El Gamal, A. Sangiovanni-Vincentelli, A.; Proceedings of the IEEE; Vol. 81; Issue 7; Jul. 1993.
- “FPGA Design Methodology for Industrial Control Systems—A Review“; Monmasson, E. Cirstea, M.N.; IEEE Transactions on Industrial Electronics; Vol 54; Issue 4; Aug. 2007.
- “A Real/Complex Logarithmic Number System ALU“; Arnold, M.G. Collange, S.; IEEE Transactions on Computers; pp. 202; Vol. 60 Issue 2; Feb. 2011.
- “Design and Implementation of an Arithmetic Processor Unit Based on the Logarithmic Number System“; Carrillo, S. Carrillo, H. Viveros, F.; IEEE Latin America Transactions (Revista IEEE America Latina); Vol 8; issue 6; pp. 605; Dec. 2010.
- “An HIL-Based Reconfigurable Platform for Design, Implementation, and Verification of Electrical System Digital Controllers“; Karimi, S. Poure, P. Saadate, S.; IEEE Transactions on Industrial Electronics; pp. 1226; Vol. 57 Issue 4; Apr. 2010.
- “A guide to migrating from microprocessor to FPGA: coping with the support tool limitations“; E.A.Bezerra and M.P.Gough; Microprocessors and Microsystems; Vol 23; pp 561-572; March 2000.
- “A survey of dynamically reconfigurable FPGA devices“; Donthi, S. Haggard, R.L.; System Theory, 2003.; pp. 422; Mar. 2003.
- “Reconfigurable computing architecture survey and introduction“; Azarian, A. Ahmadi, M.; ICCSIT 2009; pp. 269; 8-11 Aug. 2009.
- “FPGA supercomputing platforms: A survey“; Awad, M.; FPL 2009; pp. 564; Aug. 2009.
- “HW acceleration for FPGA-based drive controllers“; S. Ben Othman et. al.; ISIE 2010; pp. 196; Jul. 2010.
- “Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs“; Straka, M. Kastil, J. Kotasek, Z.; DDECS 2010; Apr. 2010.
- “Hardware design of independent experimental platform based on FPGA“; Hu Haoran Wu Jiani Zhang Fei; ICCSNA 2010; Jun. 2010.
- “FPGA Design Methodology for Industrial Control Systems—A Review“; Monmasson, E. Cirstea, M.N.; IEEE Transactions on Industrial Electronics; Vol. 54; Issue 4; Aug. 2007.
- “A modularized FPGA-based embedded system development platform“; Yu-Tsang Chang et. al.; IEEE IECON 2010; pp. 1697; Nov. 2010.
- “Creation of Partial FPGA Configurations at Run-Time“; Silva, M.L. Ferreira, J.C.; DSD 2010; pp. 80; Sept. 2010.
- “Low power State Machine design on FPGAs“; Saleem, A. Khan, S.A.; ICACTE 2010; Aug. 2010.
- “Design of high speed data acquisition system based on FPGA and DSP“; Zhang Baofeng Wang Ya Zhu Juncha ; ICAie 2010; pp. 132; Oct. 2010.
- “UCORE: Reconfigurable Platform for Educational Purposes“; F.J. Quiles et. al.; ReConFig 2010; Dec. 2010.
- “iBoard: A highly-capable, high-performance, reconfigurable FPGA-based building block for flight instrument digital electronics“; He, Yutao Ashtijou, Mohammad; NASA/ESA AHS 2010; pp. 73; June 2010.
- “Faults Coverage Improvement Based on Fault Simulation and Partial Duplication“; J. Borecky et. al.; DSD 2010; pp. 380; Sept. 2010.
- “Rapid development of space applications with responsive digital electronics board and LabVIEW FPGA“; M. McMickell et. al.; NASA/ESA AHS 2010; pp. 79; June 2010.
- “A biomimetic model for bats’ echolocation signal processing and it’s implementation on FPGA“; Binbin Cheng Fei Yang Jing Xu; ICSPS 2010; Jul. 2010.
- “A direct bitstream manipulation approach for Virtex4-based evolvable systems“; Cancare, F. Santambrogio, M.D. Sciuto, D.; ISCAS 2010; pp. 853; Jun. 2010.
- “Design of combinational logic training system using FPGA“; Sothong, S. Chayratsami, P.; IEEE Frontiers in Education (FIE); Oct. 2010.
- “Design and Implementation of HDLC Protocol and Manchester Encoding Based on FPGA in Train Communication Network“; Guozheng Li Nanlin Tan; ICIC 2010; pp. 105; Jun. 2010.
- Raffelsieper, M.; Mousavi, M.R.; Sleuters, J., “Process Algebra as a Common Framework for Hardware/Software Coverification,” IEEE Embedded Systems Letters, vol.3, no.1, pp.9,12, March 2011.
- “Applying Model-Checking to Post-Silicon-Verification: Bridging the Specification-Realisation Gap“; Dahmoune, O. de B Johnston, R.; ReConFig 2010; Dec. 2010.
- “Area-efficient FPGA logic elements: Architecture and synthesis“; J.H. Anderson, Qiang Wang; Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific; pp. 369-375; Jan. 2011
- “Efficient absolute difference circuits in Virtex-5 FPGAs“;S. Perri, P. Zicari, P. Corsonello; MELECON 2010 – 2010 15th IEEE Mediterranean Electrotechnical Conference, pp. 309-313; Apr 2010
- “Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems“; Abramovici, M.; Emmert, J.M.; Stroud, C.E.; The Third NASA/DoD Workshop on Evolvable Hardware, 2001, pp.73-92, 2001
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