EEL 510389 – Digital Systems and Reconfigurable Devices

Graduate Program in Electrical Engineering
Course code: EEL 510389
Course name: Digital Systems and Reconfigurable Devices
Course name (in Portuguese): Sistemas Digitais e Dispositivos Lógicos Reconfiguráveis
Credits: 4
Professor: Eduardo Augusto Bezerra
Term: 2020/1 - Monday 17:10-18:00-18:50-19:40-20:30

Syllabus

Introduction to digital systems; Combinational and sequential circuits; Digital systems design at the register transfer level (RTL); CPU classical model with datapath and control unit; Reconfigurable devices; Digital systems prototyping.

Ementa

Conceitos introdutórios de sistemas digitais; Circuitos combinacionais e sequenciais; Projeto de sistemas digitais no nível de transferência entre registradores (RT); Modelo clássico de CPU com bloco de dados e bloco de controle; Dispositivos lógicos reconfiguráveis; Prototipação de sistemas digitais.

Methodology

  • The contents will be introduced through lectures with the aid of multimedia resources.
  • Laboratory sessions where the students follow tutorials provided by the lecturer with instructions for using tools and development boards.
  • Reading and discussion of classical and state-of-the-art scientific papers.
  • Presentation of seminars prepared by the students.
  • The supporting texts and source codes used in the lectures and in the laboratory sessions are available on the course’s page and on the Moodle platform.
  • Hardware Description Languages (HDLs) will be used throughout the course to describe the circuits and digital systems presented.

Synopsis

  1. Introduction
    • Combinational circuits
    • Sequential circuits
    • Reconfigurable logics
    • The design flow of digital systems using EDA tools
  2. Digital systems and hardware description languages
    • Boolean Algebra and Boolean Expressions
    • Encoders, Decoders, Multiplexers, Demultiplexers
    • Arithmetic circuits, adders, comparators, counters, shifters, multipliers
    • Arithmetic and Logic Unit (ALU): synthesis and simulation with a hardware description language
  3. Sequencial circuits and controllers
    • Latches and flip-flops
    • Finite State Machines (FSMs)
    • Controllers design using FSMs
    • FSMs synthesis using a hardware description language
  4. Case study
    • Datapath and control unit design for a processing unit
    • Register Transfer Level (RTL) description of a processing unit using a hardware description language
    • Simulation, logical synthesis, physical synthesis, and hardware prototyping of a processing unit

Student assessment

  • The final grade (FT) is calculated through the geometric mean: FT = sqrt(P x S), where P is the end-of-term project grade, and S is the grade for the preparation/presentation of the seminars.
  • Pass conditions: class attendance > 75% and FT >= 7,0

Reading list

  • David A. Patterson, John L. Hennessy, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, Morgan Kaufmann, 2017.
  • Frank Vahid, “Digital Design”, 1st ed., Wiley, 2007.
  • Eduardo Bezerra and Djones Lettnin, “Synthesizable VHDL Design for FPGAs“, Springer, 2014.
  • Randy Katz, Gaetano Borrielo, “Contemporary Logic Design””, 2nd ed., Prentice Hall, 2005.
  • John F. Wakerly, “Digital design: Principles and practices”, Prentice Hall, 2005.
  • Volnei A. Pedroni, “Circuit Design with VHDL”, The MIT Press, 2004.
  • Frank Vahid, “VHDL for Digital Design”, 1st ed., Wiley, 2007.
  • Pong P. Chu, “FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version”, Wiley-Interscience, 2008.

 

Supporting tools

End-of-term project

  • TBD

Schedule

Lecture Contents
1 Digital systems and VHDL synthesis for FPGAs:
2 Digital systems and VHDL synthesis for FPGAs:
3 Digital systems testing and VHDL Test Benches:
4 Sequential circuits and FSMs:

  • Sequential circuits and FSMs described in VHDL [slides]
  • Case study: Vending machine controller [slides].

Supporting papers:
5
  • Functional description of contemporary architecture – The RISC-V case study: instruction set, registers, and addressing modes.
  • Seminars: Slides presentation – Chapter 2 of the Patterson and Hennessy book “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”.
6 RISC-V case study:
7 RISC-V case study:

  • Ripes: RISC-V simulator. The Ripes simulator (available on github), can be used not only to simulate RISC-V programs executions, but also as an assembler for the instructions (to generate the binary code for the instructions).
8
  • Seminars: Presentations describing the instructions execution in the RISC-V architecture, using slides 25 to 27 of Chapter 4 (pages 510 to 515 of Patterson e Hennessy “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”). The students must find out the binary codes for the instructions listed next, and explain all the activities performed by the architecture (datapath and control unit) during a single instruction execution. The explanation must consider a single-cycle RISC-V architecture.
    add x19, x0, x1 addi x20, x20, -32 sub x2, x19, x3
    sub x4, x1, x5 and x5, x1, x4 or x7, x8, x9
    ld x1, 0(x2) ld x2, 8(x0) ld x4, 16(x0)
    sd x3, 24(x0) sd x15,100(x2) blt x22, x20, 64
    beq x1, x3, 16 beq x1, x0, 40
9
  • Seminars: Presentations describing the instructions execution in the RISC-V architecture, using slide 72 of Chapter 4 (pages 542 to 600 of Patterson e Hennessy “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”). The students must find out the binary codes for the instructions listed next, and explain all the activities performed by the architecture (datapath and control unit). The explanation must consider a multi-cycle (pipeline) RISC-V architecture.
    add x19, x0, x1 addi x20, x20, -32 sub x2, x19, x3
    sub x4, x1, x5 and x5, x1, x4 or x7, x8, x9
    ld x1, 0(x2) ld x2, 8(x0) ld x4, 16(x0)
    sd x3, 24(x0) sd x15,100(x2) blt x22, x20, 64
    beq x1, x3, 16 beq x1, x0, 40
10 End-of-term project definition – Discussion on the expected architecture for the end-of-term project (memories, I/O, datapath, control unit).Exercises:

  • VHDL implementation and ModelSim simulation of the fetch instructions unit, shown in the block diagram on slide 13 (Chapter 4). This development will result in a better understanding of the remaining slides (14 to 27), and also the basic concepts of RISC-V presented in the previous classes.
  • VHDL implementation and ModelSim simulation of the instructions memory shown in slide 13.
  • VHDL implementation and ModelSim simulation of the data memory shown in slide 15.
  • VHDL implementation and ModelSim simulation of the registers file shown in slide 14.
  • VHDL implementation and ModelSim simulation of the ALU shown in slide 14 (see the ALU’s operation table in slide 21).
  • VHDL implementation and ModelSim simulation of the full datapath shown in slide 20.
  • The Ripes simulator (available on github), can be used not only to simulate RISC-V programs executions, but also as an assembler for the instructions (to generate the binary code for the instructions).
11
  • ??/??/2021 – Seminars – selected papers presentations – To be defined.

 
12 End-of-term project (10%): Technical report describing the proposed RISC-V architecture, including block diagrams of the datapath and control unit. The block diagrams must be prepared by the students. Slides/book copies will not be considered!
13 End-of-term project (10%): VHDL + testbench of the datapath (source codes and technical report updated).
14 End-of-term project (10%): VHDL + testbench of the control unit (source codes and technical report updated).
15 End-of-term project (20%): VHDL + testbench of the datapath and control unit integration (source codes and technical report updated).
16 End-of-term project (30%): Demonstration of RISC-V assembly programs running in the developed architecture, and implemented in an FPGA development kit (source codes and technical report updated).
17 End-of-term project (20%): Final report upload in the Moodle platform. The final report must include also the user’s guide and the datasheet).

2020/1 Schedule – Seminars and End-or-term project deliveries:

  • 26/10 – Seminars – RISC-V pipeline.
  • 09/11 – Seminars – Research papers.
  • 16/11 – [10%] Technical report – preliminary.The block diagrams used in the text must be prepared by the students. Slides/book copies will not be considered!
  • 23/11 – [10%] VHDL + testbench of the datapath.
  • 30/11 – [10%] VHDL + testbench of the control unit.
  • 07/12 – [20%] VHDL + testbench of the datapath and control unit integration.
  • 14/12 – [30%] Demonstration of the proposed RISC-V implementation in a simulator.
  • 17/12 – [20%] Final report upload in the Moodle platform.

 

Seminars 2020/1:

  • 17:15-17:30 – Brenda Ribeiro:
    1. “FPGA Implementation of Floating Point Based Cuckoo Search Algorithm“, IEEE Access, 2019.
    2. “Validation Techniques for Fault Emulation of SRAM-based FPGAs“, IEEE Transactions on Nuclear Science, 2015.
  • 18:00-18:15 – Edilberto Costa Neto:
    1. “Design of a High Accuracy and Real-Time Indoor Positioning System Based on Coding Point Identification and its FPGA Implementation“, 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2020.
    2. “Design and Implementation of Real-Time Localization Algorithms Based on FPGA for Positioning and Tracking“, IEEE Eurasia Conference on IOT, Communication and Engineering (ECICE), 2019
  • 20:15-20:30 – Vitor Spagnol:
    1. “”
    2. “”

 

Reference papers for seminars (last update in 2015):