EEL 510389 – Digital Systems and Reconfigurable Devices

Prof. Eduardo Augusto Bezerra

The goal of the project is to design and implement a dual-lockstep architecture for fault detection. The architecture must be based on a RISC-V pipeline as described in Chapter 4 of the book: David A. Patterson, John L. Hennessy, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, Morgan Kaufmann, 2017. The following requirements must be followed in the design and implementation of the architecture.

• It must be described in VHDL, implementing the base integer instruction set, 32-bit (RV32), targeting FPGA synthesis.
  
• The design should follow the basic block diagram shown in Slide 76 of Chapter_04-RISC-V.ppt.
• It must be a 5 stages pipeline architecture (IF, ID, EX, MEM and WB) with, at least, data hazard basic functionalities also implemented in VHDL.
• Any RISC-V implementation can be used as a template as, for instance, the HF-RISC implementation by Sergio Johann (GSE/PUCRS). In this case, extra hardware must be created in order to implement the additional pipeline stages and also the hazard management units.
• Alternatively, the whole VHDL for the proposed architecture can be developed from scratch, but it is not recommended considering the available time.
  
• The expected components are shown in Figure 1. The memories must store exactly the same programs, and the two RISC-V processors must read the instructions from the memories in a synchronised way. At each “step”, the results must be compared by the “Comparator” component. In case of an error, the RISC-V processors must be reset.
• The Comparator component must be defined and designed by the students, as well as all its inputs and outputs, including their sizes. For instance, the students must define the level of detail the Comparator component will provide. It is expected that it provides at least the location of the detected error (memory address?).
  
• The students must make changes in the RISC-V architecture in order to generate the “Lockstep-out” outputs. However, the proposed RISC-V must remain compatible with the RISC-V ISA standard in order to run binary code generated by commercial tools.
• In order to test the VHDL design, each student must write three different assembly programs:
  • A “test program” that uses all the instructions (with no specific functionality);
  • A useful program that must have, at least, one data hazard situation (e.g. scalar product of vectors, …); and
  • A program with injected faults (in the instructions or data) in order to trigger the fault detection mechanism.
• The programs must be written in assembly, and the binary code must be generated using the Ripes tool.
• The architecture must run not only the three programs, but also the programs developed by the other students in the class.

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Minimal instruction set to be implemented

(see RISC-V Reference Data Card, pg. 1656)

• Load immediate / jumps
  • Load immediate – lui rd, imm
  • Jump and link – jal rd, offset
  • Jump and link register – jalr rd, rs1, offset
• Branches
  • Branch on equal – beq rs1, rs2, offset
  • Branch on not equal – bne rs1, rs2, offset
  • Branch less than – blt rs1, rs2, offset
  • Branch greater than equal – bge rs1, rs2, offset
• Loads
  • Load byte – lb rd, offset(rs1)
  • Load word – lw rd, offset(rs1)
• Stores
  • Store byte – sb rs2, offset(rs1)
  • Store word – sw rs2, offset(rs1)
• Register-immediate operations
  • Addition immediate – addi rd, rs1, imm
  • AND immediate – andi rd, rs1, imm
  • XOR immediate – xori rd, rs1, imm
  • OR immediate – ori rd, rs1, imm
• Register-register operations
  • Addition – add rd, rs1, rs2
  • Subtract – sub rd, rs1, rs2
  • AND – and rd, rs1, rs2
  • XOR – xor rd, rs1, rs2
  • OR – or rd, rs1, rs2
  • Shift left logical – sll rd, rs1, rs2
  • Shift right logical – srl rd, rs1, rs2
  • Set less than – slt rd, rs1, rs2

Figure 1. Block diagram of the proposed dual-lockstep pipeline RISC-V-based architecture.