EEL 510389 – Digital Systems and Reconfigurable Devices

Graduate Program in Electrical Engineering (PPGEEL)
Course code: EEL 510389
Course name: Digital Systems and Reconfigurable Devices
Course name (in Portuguese): Sistemas Digitais e Dispositivos Lógicos Reconfiguráveis

Undergraduate – Electrical Engineering (EEL)
Course code: EEL 7838
Course name: Project Level I in Electronics III
Course name (in Portuguese): Projeto Nível I em Eletrônica III

Credits: 4
Professor: Eduardo Augusto Bezerra
Term: 2025/1 - Mondays 18:00-18:50-19:40-20:30-21:20

Syllabus

Introduction to digital systems; Combinational and sequential circuits; Digital systems design at the register transfer level (RTL); CPU classical model with datapath and control unit; Reconfigurable devices; Digital systems prototyping.

Ementa

Conceitos introdutórios de sistemas digitais; Circuitos combinacionais e sequenciais; Projeto de sistemas digitais no nível de transferência entre registradores (RT); Modelo clássico de CPU com bloco de dados e bloco de controle; Dispositivos lógicos reconfiguráveis; Prototipação de sistemas digitais.

Methodology

  • The contents will be introduced through lectures with the aid of multimedia resources.
  • Laboratory sessions where the students follow tutorials provided by the lecturer with instructions for using tools and development boards.
  • Reading and discussion of classical and state-of-the-art scientific papers.
  • Presentation of seminars prepared by the students.
  • The supporting texts and source codes used in the lectures and in the laboratory sessions are available on the course’s page and on the Moodle platform.
  • Hardware Description Languages (HDLs) will be used throughout the course to describe the circuits and digital systems presented.

Synopsis

  1. Introduction
    • Combinational circuits
    • Sequential circuits
    • Reconfigurable systems
    • The design flow of digital systems using EDA tools
  2. Digital systems and hardware description languages
    • Boolean Algebra and Boolean Expressions
    • Encoders, Decoders, Multiplexers, Demultiplexers
    • Arithmetic circuits, adders, comparators, counters, shifters, multipliers
    • Arithmetic and Logic Unit (ALU): synthesis and simulation with a hardware description language
  3. Sequential circuits and controllers
    • Latches and flip-flops
    • Finite State Machines (FSMs)
    • Controllers design using FSMs
    • FSMs synthesis using a hardware description language
  4. Case study
    • Datapath and control unit design for a processing unit
    • Register Transfer Level (RTL) description of a processing unit using a hardware description language
    • Simulation, logical synthesis, physical synthesis, and hardware prototyping of a processing unit

Student assessment

  • The final grade (FG) is calculated through the geometric mean: FG = sqrt(P x A), where P is the end-of-term project grade, and A is the grade for the mid-term assessment.
  • Pass conditions:
    • EEL 510389 students: class attendance > 75% and FT >= 7,0
    • EEL 7838 students: class attendance > 75% and FT >= 6,0

Reading list

  • David A. Patterson, John L. Hennessy, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, Morgan Kaufmann, 2020.
  • Frank Vahid, “Digital Design”, 1st ed., Wiley, 2007.
  • Eduardo Bezerra and Djones Lettnin, “Synthesizable VHDL Design for FPGAs“, Springer, 2014.
  • Randy Katz, Gaetano Borrielo, “Contemporary Logic Design””, 2nd ed., Prentice Hall, 2005.
  • John F. Wakerly, “Digital design: Principles and practices”, Prentice Hall, 2005.
  • Volnei A. Pedroni, “Circuit Design with VHDL”, The MIT Press, 2004.
  • Frank Vahid, “VHDL for Digital Design”, 1st ed., Wiley, 2007.
  • Pong P. Chu, “FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version”, Wiley-Interscience, 2008.

 

Supporting tools

Schedule

Week Contents
1 Digital systems and VHDL synthesis for FPGAs:
2 Digital systems and VHDL synthesis for FPGAs:
3 Introduction to reconfigurable devices:
4 Digital systems testing and VHDL Test Benches:
5 Sequential circuits and FSMs:

  • Sequential circuits and FSMs described in VHDL [slides]
  • Case study: Vending machine controller [slides].

Supporting papers:
6 Mid-term assessment.
7 No class – Holiday
8 RISC-V case study

  • Functional description of a contemporary architecture – The RISC-V architecture: instruction set, registers, and addressing modes.
  • Patterson and Hennessy book “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”.
  • Patterson and Hennessy: Chapter 4 – slides 49 to 76:
    • single-cycle: slides 49 to 57
    • multi-cycle: slides 58 to 63
    • forwarding 1: slides 64 to 66
    • forwarding 2: slides 67 to 69
    • forwarding 3: slides 70 to 72
    • hazard: slides 73 to 76
 9 RISC-V architecture – instructions execution 

Presentations describing the execution of the instructions in the RISC-V architecture, using slide 72 of Chapter 4 (pages 542 to 600 of Patterson e Hennessy “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”). The students must find out the binary codes for the instructions listed next, and explain all the activities performed by the architecture (datapath and control unit). The explanation must consider a multi-cycle (pipeline) RISC-V architecture, using a VHDL implementation to show where in the code the respective instruction is described (which parts of the VHDL hardware are exercised by the instruction).

Sem. 1 add x19, x0, x1 ld x1, 0(x2) blt x2, x3, 32
Sem. 2 addi x20, x20, -32 sd x3, 24(x0) beq x1, x3, 16
Sem. 3 sub x4, x1, x5 ld x4, 16(x0) blt x4, x5, 40
Sem. 4 add x2, x19, x3 sd x15, 100(x2) beq x5, x6, 8
Sem. 5 and x5, x1, x4 ld x2, 8(x0) blt x6, x4, 4
Sem. 6 addi x4, x2, 12 sd x1, 10(x3) beq x1, x0, 40

 
10 RISC-V case study – papers discussion
11 End-of-term project definition – Discussion on the expected architecture for the end-of-term project (memories, I/O, datapath, control unit). 

RISC-V Tools:

  • Ripes: RISC-V simulator. The Ripes simulator (available on Github), can be used not only to simulate RISC-V program executions, but also as an assembler for the instructions (to generate the binary code for the instructions).
  • GHDL – Analyzer, compiler, simulator and synthesizer for VHDL. GHDL is not an interpreter: it allows you to analyse and elaborate sources for generating machine code from your design.
12 End-of-term project – Discussion on the expected architecture for the end-of-term project (memories, I/O, datapath, control unit). 

Exercises:

  • VHDL implementation and ModelSim simulation of the fetch instructions unit, shown in the block diagram on slide 13 (Chapter 4). This development will result in a better understanding of the remaining slides (14 to 27), and also the basic concepts of RISC-V presented in the previous classes.
  • VHDL implementation and ModelSim simulation of the instructions memory shown in slide 13.
  • VHDL implementation and ModelSim simulation of the data memory shown in slide 15.
  • VHDL implementation and ModelSim simulation of the registers file shown in slide 14.
  • VHDL implementation and ModelSim simulation of the ALU shown in slide 14 (see the ALU’s operation table in slide 21).
  • VHDL implementation and ModelSim simulation of the full datapath shown in slide 20.
13 End-of-term project – Discussion on the expected architecture for the end-of-term project (memories, I/O, peripherals, datapath, control unit).
14 End-of-term project (10%): Technical report – preliminary. The block diagrams used in the text must be prepared by the students. Slides/book copies will not be considered!
15 End-of-term project (10%): VHDL + testbench of the datapath.
16 End-of-term project (10%): VHDL + testbench of the control unit.
17 End-of-term project (20%): VHDL + testbench of the datapath and control unit integration.
18 End-of-term project (50%): Demonstration of the proposed RISC-V implementation in a simulator, and final report upload in the Moodle platform.
19 Reserved.

 

Papers presented in past editions (last update in 2021):