Eduardo Augusto Bezerra, PhD

Special Topics in Digital Systems and Computer Architecture I – 34637-01

“Test of Digital Systems”

Fall 2005/2

Catholic University of RS (PUCRS), Informatics Faculty/PPGCC

Prof. Eduardo Bezerra

Lectures: Tue 09:50-11:30 am, room 106.18 (PPGCC)

Summary course info:

Goals (see PRG_34637.doc, in Portuguese, for course details):
- To introduce and to discuss basic concepts related to test technology and fault tolerance in digital systems
- To study test techniques and strategies, aiming system reliability improvement
- To allow students modeling case studies and implementing them on prototyping platforms

Course Evaluation
- Article discussion: 20%
- Seminars: 30%
- Term Project and Paper: 50%

Date	Contents	Reading	Assignment
Tue 09/08	NO CLASS	Recommended reading: Article 1 - “Dependable Computing Concepts and Fault Tolerance Terminology”, Jean-Claude Laprie Required reading: Article 2 - “Fundamental Concepts of Computer System Dependability”, Algirdas Avizienis, Jean-Claude Laprie and Brian Randell	Preparation for article discussion.
Tue 16/08 (2 h)	Course intro and article discussion.	Required reading: Article 2, Avizienis Recommended reading: Article 1, Laprie	Article discussion
Tue 23/08 (2 h)	Article discussion (cont.). Test of digital systems (intro).	Required reading: Article 2, Avizienis Recommended reading: Article 1, Laprie Recommended reading: Lecturer Notes, Bezerra (in Portuguese)	Article discussion
Tue 30/08	NO CLASS – PPGCC Workshop	Required reading: Lecturer Notes, Bezerra (in Portuguese)
Tue 06/09	NO CLASS – SBCCI.	Required reading: Lecturer Notes, Bezerra (in Portuguese)
Tue 13/09 (2 h)	Test of digital systems (cont.).	Required reading: Lecturer Notes, Bezerra, in Portuguese, "Teste de Sistemas Digitais". Recommended reading: Slides from Zebo Peng's Digital Systems Test course [Fault modeling and simulation, automatics test pattern generation, principles of design for testability (DFT), testability analysis, test synthesis, testability issues in SW and HW, test issues in SOCs, on-line testing and built-in self-test (BIST)].	Article discussion
Tue 20/09	NO CLASS - Holiday
Tue 27/09 (2 h)	Test methodology.	Required reading: Lecturer Notes, Bezerra, in Portuguese, "Metodologias de Teste Funcional para Microprocessadores".	Article discussion
Tue 04/10 (2 h)	Term project definition and discussion.	Group I: "Functional testing of microprocessors"; Aline, Rosana and Carlos. Group II: "Memory testing, test execution and management"; Marcio, Gabriel and Ries.	Tasks and project activities.
Tue 11/10 (2 h)	Test methodology (cont.) and seminars.	Aline Vieira de Mello, seminar: “Pseudo-online testing methodologies for various components of field programmable gate arrays” Carlos Adail Scherer Junior, seminar: “Soft Errors in Advanced Computer Systems”	Seminars
Tue 18/10 (2 h)	Test methodology (cont.) and seminars.	Luis Henrique Leal Ries, seminar: “Online BIST and BIST-Based Diagnosis of FPGA Logic Blocks” Gabriel Marquesan Almeida, seminar: "Parallel Decoding Cyclic Burst Error Correcting Codes" Rosana Perazzolo Disconzi, seminar: "IP Cores Testing" Marcio Garcia Martins, seminar: “”	Seminars
Tue 25/10	Term project implementation - NO CLASS
Tue 01/11	Term project implementation - NO CLASS
Tue 08/11	Term project implementation - NO CLASS
Tue 15/11	NO CLASS - Holiday
Tue 22/11	Term project implementation - NO CLASS
Tue 29/11	Term project implementation - NO CLASS
Tue 06/12 (2 h)	Term project and paper presentation.	Group I: "Functional testing of microprocessors"; Aline, Rosana and Carlos. Group II: "Memory testing, test execution and management"; Marcio, Gabriel and Ries.	Term project and paper presentation
Tue 13/12	NO CLASS

Note: dates and topics are subject to change.

Literature:

1. FUJIWARA, H. Logic Testing and Design for Testability. Cambridge: MIT Press, 1985. 284p.

2. ABRAMOVICI, M.; BREUER, M. A.; and FRIEDMAN, A. D. Digital Systems Testing and Testable Design. Computer Science Press, 1990

3. PRADHAN, D. K. Fault-Tolerant Computer System Design. Prentice-Hall, 1996. 544p

4. HAYES, J.P. Fault Modeling. IEEE Design and Test of Computers, New York, v.2, n.2, p.88-95, Apr. 1985.

5. LAPRIE, J.C. Dependable computing and fault-tolerance: concepts and terminology. In: INTERNATIONAL SYMPOSIUM ON FAULTTOLERANT COMPUTING, 15., 1985, New York.

6. RUSSEL, G.; SAYERS, I.L. Advanced Simulation and Test Methodologies for VLSI Design. London: Van Nostrand Reinhold, 1989. 378p.

7. SIEWIOREK, D.P.; SWARZ, R.S. The Theory and Practice of Reliable System Design. Bedford: Digital Press, 1982. 772 p.

8. DAVID, R. Randon Testing of Digital Circuits: Theory and Applications. Marcel Dekker Inc., New York, 1998. 475 p.

9. STROUD, C. E. A Designer's Guide to Built-In Self-Test. Kluwer Academic Publishers, Norwell, Massachusetts, 2002. 318 p.

10. NICOLAIDS, M.; ZORIAN, Y.; PRADHAN, D.K. (editors) On-line Testing for VLSI, Kluwer Academic Publishers, Norwell, Massachusetts, 1998. 159 p.

11. RAJSUMAN, R. System-on-a-Chip: Design and Test, Artech House signal processing library, Santa Clara, USA, 2000. 277 p.

13. BEZERRA, E. A.; VARGAS, F.; GOUGH, M. P. Improving reconfigurable systems reliability by combining periodical test and redundancy techniques: a case study. Journal of Electronic Testing: Theory And Applications - JETTA, Norwell, Ma, Usa, v.17, n.3, p.701-711, 2001.

14. BEZERRA, E. A.; VARGAS, F.; JANSCH-PORTO, I.; Kitajima, J. P. Implementing transparent BIST for embedded memories: the transputer case study. Journal of Solid State Devices And Circuits, Sao Paulo, v.15, n.1, p.14-19, 1997.

15. BEZERRA, E. A.; VARGAS, F.; OZCERIT, A.; GOUGH, M. P. Improving the dependability of embedded systems using configurable computing technology. In: ISCIS’99 - XIV. INTERNATIONAL SYMPOSIUM ON COMPUTER AND INFORMATION SCIENCES, Izmir, Turkey, 1999. p.49-56.

16. VARGAS, F.; BEZERRA, E. A.; WULFF, L.; BARROS JR, D. Reliability verification of digital systems design based on mutation analysis. In: 7th IEEE ASIAN TEST SYMPOSIUM - ATS’98, 1998, p.52-57.

12. Lecture notes

13. Selected scientific articles