------------------------------------------------------------------------ SpaceCAN (c) 2000 by Eduardo Augusto Bezerra, version 0.1beta. It is free for non-commercial use. ------------------------------------------------------------------------ This directory contains some modules of SpaceCAN which is a Controller Area Network (CAN) implemented in VHDL for synthesis, according to the CAN specification 2.0A. SpaceCAN will have optional modules to increase some of its dependability features, targeting space applications. SpaceCAN is a new project and only a couple of modules are available for download. ------------------------------------------------------------------------ USER IDENTIFICATION Please, fill in the following fields before proceeding. A personal password to open some of the files will be sent to the email address given. Name: Email: Organization: Country: ------------------------------------------------------------------------ DOWNLOAD Module for building data frames for transmission. Warning!! This module has to be synthesised using TxDataFrame.zip (or download from Synplify, in order to the RAM blocks UK) be inferenced. The module uses two FIFOs for buffering input and output data. The FIFOs are larger than the necessary, and are used for test only. CRC_GEN_EA.vhd (or download from UK) CRC generator for the transmitter and receiver modules. crc_applet.zip (or download from UK) A Java applet developed to test the CRC generator module. index.html (or download from UK) This file. index.txt (or download from UK) Text version of this file. ------------------------------------------------------------------------ HOW TO INSTALL AND RUN IT There is no installation program. Just download the files into an empty folder and unzip them. Synplify has been used for the logical synthesis, and Active-VHDL for the simulation. The style used for the VHDL programming allows the modules to be used in FPGAs from different manufactures, but unfortunately, in order to achieve good synthesis results, it is recommended the use of Synplify. Minor modifications in the vHDL code may be necessary, in case of using another tool for the logical synthesis. The following is the project file used by Synplify to synthesise the TxDataFrame module (see TxDataFrame.zip). The file data_frame_gen_ea.vhd contains the main entity/architecture pair. #-- Synplicity, Inc. #-- Synplify version 5.0.8 #-- Project file N:\Sussex\Projects\Can\Data_frame\Synplify\data_frame.prj #-- Written on Thu Apr 13 12:29:01 2000 #device options set_option -technology Virtex set_option -part XCV300 set_option -package BG352 set_option -speed_grade -4 #add_file options add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/can_p.vhd" add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/ram256x16_mem_ea.vhd" add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/ram256x8_mem_ea.vhd" add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/fifo_df_out_ea.vhd" add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/fifo_df_in_ea.vhd" add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/crc_gen_ea.vhd" add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/data_frame_ea.vhd" add_file -vhdl -lib work "n:/sussex/projects/can/data_frame/src/data_frame_gen_ea.vhd" #compilation/mapping options set_option -default_enum_encoding onehot set_option -symbolic_fsm_compiler false set_option -resource_sharing true #map options set_option -frequency 0.000 set_option -fanout_limit 100 set_option -maxfan_hard false set_option -force_gsr true set_option -disable_io_insertion false set_option -xilinx_m1 true #set result format/file last project -result_format "xnf" project -result_file "n:/sussex/projects/can/data_frame/src/data_frame_gen_ea.xnf" ------------------------------------------------------------------------ BUG REPORTS Please send comments and bug reports to: E.A.Bezerra@sussex.ac.uk or eduardob@inf.pucrs.br ------------------------------------------------------------------------ !!!!!!!!!!! NO WARRANTY !!!!!!!!!!! SpaceCAN is still under development! ------------------------------------------------------------------------ CONTACT ADDRESSES Eduardo Augusto Bezerra, Lecturer Eduardo Augusto Bezerra, PhD student in Computer Science Space Science Centre GAPH - Grupo de Apoio ao Projeto School of Engineering and Information de Hardware Technology Faculdade de Informatica University of Sussex Pontificia Universidade Catolica Brighton do Rio Grande do Sul - PUCRS BN1 9QT Av. Ipiranga, 6681 UK CEP 90619-900 Porto Alegre - RS e-mail: E.A.Bezerra@sussex.ac.uk Brasil http://www.sussex.ac.uk/engg/research/space/ e-mail: eduardob@inf.pucrs.br Phone: +44 (0)1273 877086 http://www.inf.pucrs.br/~eduardob Fax: +44 (0)1273 678399 ENGG II - room 4B11 Phone: +55 (0)51 320-4181 Fax: +55 (0)51 339-1564 ------------------------------------------------------------------------