IDIV - Signed Integer Division
Usage: IDIV src
Modifies Flags: (AF,CF,OF,PF,SF,ZF undefined)
Signed binary division of accumulator by source. If source is a byte value, AX is divided by "src" and the quotient is stored in AL and the remainder in AH. If source is a word value, DX:AX is divided by "src", and the quotient is stored in AL and the remainder in DX.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
reg8 | 17 | 19 | 19 | 2 |
reg16 | 25 | 27 | 27 | 2 |
reg32 | 43 | 43 | 2 | |
mem8 | 20 | 22 | 20 | 2-4 |
mem16 | 38 | 30 | 28 | 2-4 |
mem32 | 46 | 44 | 2-4 |
IMUL - Signed Multiply
Usage: IMUL src
IMUL src,immed (286+)
IMUL dest,src,immed8 (286+)
IMUL dest,src (386+)
Modifies Flags: CF OF (AF,PF,SF,ZF undefined)
Signed multiplication of accumulator by "src" with result placed in the accumulator. If the source operand is a byte value, it is multiplied by AL and the result stored in AX. If the source operand is a word value it is multiplied by AX and the result is stored in DX:AX. Other variations of this instruction allow specification of source and destination registers as well as a third immediate factor.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
reg8 | 13 | 9-14 | 13-18 | 2 |
reg16 | 21 | 9-22 | 13-26 | 2 |
reg32 | 9-38 | 12-42 | 2 | |
mem8 | 16 | 12-17 | 13-18 | 2-4 |
mem16 | 24 | 12-25 | 13-26 | 2-4 |
mem32 | 12-41 | 13-42 | 2-4 | |
reg16,reg16 | 9-22 | 13-26 | 3-5 | |
reg32,reg32 | 9-38 | 13-42 | 3-5 | |
reg16,mem16 | 12-25 | 13-26 | 3-5 | |
reg16,immed | 21 | 9-22 | 13-26 | 3 |
reg32,immed | 21 | 9-38 | 13-42 | 3-6 |
reg16,reg16,immed | 2 | 9-22 | 13-26 | 3-6 |
reg32,reg32,immed | 21 | 9-38 | 13-42 | 3-6 |
reg16,mem16,immed | 24 | 12-25 | 13-26 | 3-6 |
reg32,mem32,immed | 24 | 12-41 | 13-42 | 3-6 |
IN - Input Byte or Word From Port
Usage: IN accum,port
Modifies Flags: None
A byte, word or dword is read from "port" and placed in AL, AX or EAX respectively. If the port number is in the range of 0-255 it can be specified as an immediate, otherwise the port number must be specified in DX. Valid port ranges on the PC are 0-1024, though values through 65535 may be specified and recognized by third party vendors and PS/2's.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
accum,immed8 | 5 | 12 | 14 | 2 |
accum,immed8 (PM) | 6/26 | 8/28/27 | 2 | |
accum,DX | 5 | 13 | 14 | 1 |
accum,DX (PM) | 7/27 | 8/28/27 | 1 | |
386+ protected mode timings depend on privilege
levels. first number is the timing if: CPL <= IOPL second number is the timing if: CPL > IOPL or in VM 86 mode (386) CPL >= IOPL (486) third number is the timing when: virtual mode on 486 processor 486 virtual mode always requires 27 cycles |
INC - Increment
Usage: INC dest
Modifies Flags: AF OF PF SF ZF
Adds one to destination unsigned binary operand.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
reg8 | 2 | 2 | 1 | 2 |
reg16 | 2 | 2 | 1 | 1 |
reg32 | 2 | 2 | 1 | 1 |
mem | 7 | 6 | 3 | 2-4 |
INS - Input String from Port (80188+)
Usage: INS dest,port
INSB
INSW
INSD (386+)
Modifies Flags: None
Loads data from port to the destination ES:(E)DI (even if a destination operand is supplied). (E)DI is adjusted by the size of the operand and increased if the Direction Flag is cleared and decreased if the Direction Flag is set. For INSB, INSW, INSD no operands are allowed and the size is determined by the mnemonic.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
dest,port | 15 | 7 | 1 | 1 |
dest,port (PM) | 5 | 9/29 | 10/32/30 | 1 |
none | 5 | 15 | 17 | 1 |
none (PM) | 5 | 9/29 | 10/32/30 | 1 |
386+ protected mode timings depend on privilege
levels. first number is the timing if: CPL <= IOPL second number is the timing if: CPL > IOPL third number is the timing if: virtual mode on 486 processor |
INT - Interrupt
Usage: INT num
Modifies Flags: TF IF
Initiates a software interrupt by pushing the flags, clearing the Trap and Interrupt Flags, pushing CS followed by IP and loading CS:IP with the value found in the interrupt vector table. Execution then begins at the location addressed by the new CS:IP
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
3 (constant) | 23+m | 33 | 26 | 2 |
3 (prot. mode, same priv.) | 40+m | 59 | 44 | 2 |
3 (prot. mode, more priv.) | 78+m | 99 | 71 | 2 |
3 (from VM86 to PL 0) | 119 | 82 | 2 | |
3 (prot. mode via task gate) | 167+m | TS | 37+TS | 2 |
immed8 | 23+m | 37 | 30 | 1 |
immed8 (prot. mode, same priv.) | 40+m | 59 | 44 | 1 |
immed8 (prot. mode, more priv.) | 78+m | 99 | 71 | 1 |
immed8 (from VM86 to PL 0) | 119 | 86 | 1 | |
immed8 (prot. mode, via task gate) | 167+m | TS | 37+TS | 1 |
INTO - Interrupt on Overflow
Usage: INTO
Modifies Flags: IF TF
If the Overflow Flag is set this instruction generates an INT 4 which causes the code addressed by 0000:0010 to be executed.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
none: jump | 24+m | 35 | 28 | 1 |
none: no jump | 3 | 3 | 3 | 1 |
none: (prot. mode, same priv.) | 59 | 46 | 1 | |
none: (prot. mode, more priv.) | 99 | 73 | 1 | |
none: (from VM86 to PL 0) | 84 | 119 | 1 | |
none: (prot. mode, via task gate) | TS | 39+TS | 1 |
INVD - Invalidate Cache (486+)
Usage: INVD
Modifies Flags: None
Flushes CPU internal cache. Issues special function bus cycle which indicates to flush external caches. Data in write-back external caches is lost.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
none | 4 | 2 |
INVLPG - Invalidate Translation Look-Aside Buffer Entry (486+)
Usage: INVLPG
Modifies Flags: None
Invalidates a single page table entry in the Translation Look-Aside Buffer. Intel warns that this instruction may be implemented differently on future processors.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
none | 12 | 2 | ||
timing is for TLB entry hit only. |
IRET/IRETD - Interrupt Return
Usage: IRET
IRETD (386+)
Modifies Flags: AF CF DF IF PF SF TF ZF
Returns control to point of interruption by popping IP, CS and then the Flags from the stack and continues execution at this location. CPU exception interrupts will return to the instruction that cause the exception because the CS:IP placed on the stack during the interrupt is the address of the offending instruction.
Clocks | ||||
---|---|---|---|---|
operands | 286 | 386 | 486 | Size Bytes |
(iret)none | 17+m | 22 | 15 | 1 |
(prot. mode) | 31+m | 38 | 15 | 1 |
(to less privilege) | 55+m | 82 | 36 | 1 |
(different task, NT=1) | 169+m | TS | TS+32 | 1 |
(iretd) | 22/38 | 15 | 1 | |
(to less privilege) | 82 | 36 | 1 | |
(to VM86 mode) | 60 | 15 | 1 | |
iretd (different task, NT=1) | TS | TS+32 | 1 | |
386 timings are listed as real-mode/protected mode |
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