General informations

Intel 80x86 Family Architecture

General Purpose Registers	Segment Registers
AH/AL AX (EAX) Accumulator	CS Code Segment
BH/BL BX (EBX) Base	DS Data Segment
CH/CL CX (ECX) Counter	SS Stack Segment
DH/DL DX (EDX) Data	ES Extra Segment
	(FS) 386 and newer
(Exx) indicates 386+ 32 bit register	(GS) 386 and newer

Pointer Registers	Stack Registers
SI (ESI) Source Index	SP (ESP) Stack Pointer
DI (EDI) Destination Index	BP (EBP) Base Pointer
IP Instruction Pointer

Status Register
FLAGS Status Flags (see FLAGS)

Special Registers (386+ only)
CR0 Control Register 0	DR0 Debug Register 0
CR2 Control Register 2	DR1 Debug Register 1
CR3 Control Register 3	DR2 Debug Register 2
	DR3 Debug Register 3
TR4 Test Register 4	DR6 Debug Register 6
TR5 Test Register 5	DR7 Debug Register 7
TR6 Test Register 6
TR7 Test Register 7

Register overriding

Register	Default Segment	Valid Overrides
BP	SS	DS, ES, CS
SI or DI	DS	ES, SS, CS
DI strings	ES	None
SI strings	DS	ES, SS, CS

Instruction Clock Cycle Calculation

Some instructions require additional clock cycles due to a "Next Instruction Component" identified by a "+m" in the instruction clock cycle listings. This is due to the prefetch queue being purge on a control transfers. Below is the general rule for calculating "m":

286 "m" is the number of bytes in the next instruction
386 "m" is the number of components in the next instruction (the instruction coding (each byte), plus the data and the displacement are all considered components)

Task State Calculation

"TS" is defined as switching from VM/486 or 80286 TSS to one of the following:

Old task	486 TSS (VM=0)	486 TSS (VM=1)	386 TSS (VM=0)	386 TSS (VM=1)	286 TSS
	New Task
386 TSS (VM=0)			309	226	282
386 TSS (VM=1)			314	231	287
386 CPU/286 TSS			307	224	280
486 CPU/286 TSS	199	177			180

Miscellaneous

all timings are for best case and do not take into account wait states, instruction alignment, the state of the prefetch queue, DMA refresh cycles, cache hits/misses or exception processing.
to convert clocks to nanoseconds divide one microsecond by the processor speed in MegaHertz: (1000MHz/(n MHz)) = X nanoseconds

FLAGS - Intel 8086 Family Flags Register

      |11|10|F|E|D|C|B|A|9|8|7|6|5|4|3|2|1|0|
        |  | | | | | | | | | | | | | | | | |___  CF Carry Flag
        |  | | | | | | | | | | | | | | | |___  1
        |  | | | | | | | | | | | | | | |___  PF Parity Flag
        |  | | | | | | | | | | | | | |___  0
        |  | | | | | | | | | | | | |___  AF Auxiliary Flag
        |  | | | | | | | | | | | |___  0
        |  | | | | | | | | | | |___  ZF Zero Flag
        |  | | | | | | | | | |___  SF Sign Flag
        |  | | | | | | | | |___  TF Trap Flag  (Single Step)
        |  | | | | | | | |___  IF Interrupt Flag
        |  | | | | | | |___  DF Direction Flag
        |  | | | | | |___  OF Overflow flag
        |  | | | |_____  IOPL I/O Privilege Level  (286+ only)
        |  | | |_____  NT Nested Task Flag  (286+ only)
        |  | |_____  0
        |  |_____  RF Resume Flag (386+ only)
        |______  VM  Virtual Mode Flag (386+ only)

- see PUSHF POPF STI CLI STD CLD

MSW - Machine Status Word (286+ only)

      |31|30-5|4|3|2|1|0|  Machine Status Word
        |   |  | | | | |____ Protection Enable (PE)
        |   |  | | | |_____ Math Present (MP)
        |   |  | | |______ Emulation (EM)
        |   |  | |_______ Task Switched (TS)
        |   |  |________ Extension Type (ET)
        |   |__________ Reserved
        |_____________ Paging (PG)

Bit 0 PE Protection Enable, switches processor between protected and real mode
Bit 1 MP Math Present, controls function of the WAIT instruction
Bit 2 EM Emulation, indicates whether coprocessor functions are to be emulated
Bit 3 TS Task Switched, set and interrogated by coprocessor on task switches and when interpretting coprocessor instructions
Bit 4 ET Extension Type, indicates type of coprocessor in system
Bits 5-30 Reserved
bit 31 PG Paging, indicates whether the processor uses page tables to translate linear addresses to physical addresses

-see SMSW LMSW

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