Classic Timing Analyzer report for top
Mon Jun 20 21:11:16 2011
Quartus II Version 9.1 Build 222 10/21/2009 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Parallel Compilation
  6. Clock Setup: 'CLOCK_50'
  7. tsu
  8. tco
  9. th
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                             ;
+------------------------------+-------+---------------+----------------------------------+-------------------------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                    ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------------------+----------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.530 ns                         ; KEY[0]                  ; EA.S0    ; --         ; CLOCK_50 ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 9.272 ns                         ; maior[5]                ; saida[5] ; CLOCK_50   ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.128 ns                        ; KEY[0]                  ; EA.S2    ; --         ; CLOCK_50 ; 0            ;
; Clock Setup: 'CLOCK_50'      ; N/A   ; None          ; 247.40 MHz ( period = 4.042 ns ) ; ROM:R0|Data_out[4]~reg0 ; EA.S1    ; CLOCK_50   ; CLOCK_50 ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                         ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------------------+----------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                                                           ; Near End           ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                    ; To                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 247.40 MHz ( period = 4.042 ns )               ; ROM:R0|Data_out[4]~reg0 ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.807 ns                ;
; N/A   ; 263.71 MHz ( period = 3.792 ns )               ; ROM:R0|Data_out[4]~reg0 ; EA.S0                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.682 ns                ;
; N/A   ; 271.00 MHz ( period = 3.690 ns )               ; ROM:R0|Data_out[1]~reg0 ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.475 ns                ;
; N/A   ; 271.30 MHz ( period = 3.686 ns )               ; ROM:R0|Data_out[1]~reg0 ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.471 ns                ;
; N/A   ; 275.25 MHz ( period = 3.633 ns )               ; ROM:R0|Data_out[1]~reg0 ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.418 ns                ;
; N/A   ; 276.01 MHz ( period = 3.623 ns )               ; maior[0]                ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.409 ns                ;
; N/A   ; 276.32 MHz ( period = 3.619 ns )               ; maior[0]                ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.405 ns                ;
; N/A   ; 276.55 MHz ( period = 3.616 ns )               ; ROM:R0|Data_out[7]~reg0 ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.594 ns                ;
; N/A   ; 279.72 MHz ( period = 3.575 ns )               ; ROM:R0|Data_out[0]~reg0 ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.360 ns                ;
; N/A   ; 279.80 MHz ( period = 3.574 ns )               ; ROM:R0|Data_out[1]~reg0 ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.359 ns                ;
; N/A   ; 280.03 MHz ( period = 3.571 ns )               ; ROM:R0|Data_out[0]~reg0 ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.356 ns                ;
; N/A   ; 280.43 MHz ( period = 3.566 ns )               ; maior[0]                ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.352 ns                ;
; N/A   ; 284.25 MHz ( period = 3.518 ns )               ; ROM:R0|Data_out[0]~reg0 ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.303 ns                ;
; N/A   ; 285.14 MHz ( period = 3.507 ns )               ; maior[0]                ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.293 ns                ;
; N/A   ; 289.10 MHz ( period = 3.459 ns )               ; ROM:R0|Data_out[0]~reg0 ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.244 ns                ;
; N/A   ; 289.35 MHz ( period = 3.456 ns )               ; EA.S2                   ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.513 ns                ;
; N/A   ; 289.86 MHz ( period = 3.450 ns )               ; EA.S2                   ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.510 ns                ;
; N/A   ; 293.77 MHz ( period = 3.404 ns )               ; ROM:R0|Data_out[3]~reg0 ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.488 ns                ;
; N/A   ; 294.46 MHz ( period = 3.396 ns )               ; ROM:R0|Data_out[2]~reg0 ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.181 ns                ;
; N/A   ; 294.81 MHz ( period = 3.392 ns )               ; ROM:R0|Data_out[2]~reg0 ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.177 ns                ;
; N/A   ; 297.09 MHz ( period = 3.366 ns )               ; ROM:R0|Data_out[7]~reg0 ; EA.S0                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.469 ns                ;
; N/A   ; 299.49 MHz ( period = 3.339 ns )               ; ROM:R0|Data_out[2]~reg0 ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.124 ns                ;
; N/A   ; 300.57 MHz ( period = 3.327 ns )               ; ROM:R0|Data_out[3]~reg0 ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.112 ns                ;
; N/A   ; 300.93 MHz ( period = 3.323 ns )               ; ROM:R0|Data_out[3]~reg0 ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.108 ns                ;
; N/A   ; 304.32 MHz ( period = 3.286 ns )               ; maior[3]                ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.072 ns                ;
; N/A   ; 304.69 MHz ( period = 3.282 ns )               ; maior[3]                ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.068 ns                ;
; N/A   ; 304.88 MHz ( period = 3.280 ns )               ; ROM:R0|Data_out[2]~reg0 ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.065 ns                ;
; N/A   ; 305.81 MHz ( period = 3.270 ns )               ; ROM:R0|Data_out[1]~reg0 ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.421 ns                ;
; N/A   ; 305.81 MHz ( period = 3.270 ns )               ; ROM:R0|Data_out[3]~reg0 ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.055 ns                ;
; N/A   ; 309.02 MHz ( period = 3.236 ns )               ; maior[4]                ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.022 ns                ;
; N/A   ; 309.41 MHz ( period = 3.232 ns )               ; maior[4]                ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.018 ns                ;
; N/A   ; 309.69 MHz ( period = 3.229 ns )               ; maior[3]                ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.015 ns                ;
; N/A   ; 309.89 MHz ( period = 3.227 ns )               ; maior[1]                ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.013 ns                ;
; N/A   ; 310.27 MHz ( period = 3.223 ns )               ; maior[1]                ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.009 ns                ;
; N/A   ; 311.43 MHz ( period = 3.211 ns )               ; ROM:R0|Data_out[3]~reg0 ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.996 ns                ;
; N/A   ; 314.56 MHz ( period = 3.179 ns )               ; maior[4]                ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.965 ns                ;
; N/A   ; 315.46 MHz ( period = 3.170 ns )               ; maior[3]                ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.956 ns                ;
; N/A   ; 315.46 MHz ( period = 3.170 ns )               ; maior[1]                ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.956 ns                ;
; N/A   ; 315.86 MHz ( period = 3.166 ns )               ; ROM:R0|Data_out[4]~reg0 ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.951 ns                ;
; N/A   ; 316.06 MHz ( period = 3.164 ns )               ; maior[2]                ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.950 ns                ;
; N/A   ; 316.26 MHz ( period = 3.162 ns )               ; ROM:R0|Data_out[4]~reg0 ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.947 ns                ;
; N/A   ; 316.46 MHz ( period = 3.160 ns )               ; maior[2]                ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.946 ns                ;
; N/A   ; 317.06 MHz ( period = 3.154 ns )               ; ROM:R0|Data_out[3]~reg0 ; EA.S0                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.363 ns                ;
; N/A   ; 320.51 MHz ( period = 3.120 ns )               ; maior[4]                ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.906 ns                ;
; N/A   ; 320.92 MHz ( period = 3.116 ns )               ; ROM:R0|Data_out[2]~reg0 ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.344 ns                ;
; N/A   ; 321.44 MHz ( period = 3.111 ns )               ; maior[1]                ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.897 ns                ;
; N/A   ; 321.65 MHz ( period = 3.109 ns )               ; ROM:R0|Data_out[4]~reg0 ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; 321.85 MHz ( period = 3.107 ns )               ; maior[2]                ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.893 ns                ;
; N/A   ; 323.94 MHz ( period = 3.087 ns )               ; ROM:R0|Data_out[1]~reg0 ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.872 ns                ;
; N/A   ; 324.04 MHz ( period = 3.086 ns )               ; ROM:R0|Data_out[1]~reg0 ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.871 ns                ;
; N/A   ; 327.87 MHz ( period = 3.050 ns )               ; ROM:R0|Data_out[4]~reg0 ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.835 ns                ;
; N/A   ; 328.08 MHz ( period = 3.048 ns )               ; maior[2]                ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.834 ns                ;
; N/A   ; 328.52 MHz ( period = 3.044 ns )               ; EA.S2                   ; endereco[0]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.307 ns                ;
; N/A   ; 328.95 MHz ( period = 3.040 ns )               ; EA.S2                   ; endereco[4]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.305 ns                ;
; N/A   ; 331.13 MHz ( period = 3.020 ns )               ; maior[0]                ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.806 ns                ;
; N/A   ; 331.24 MHz ( period = 3.019 ns )               ; maior[0]                ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.805 ns                ;
; N/A   ; 336.47 MHz ( period = 2.972 ns )               ; ROM:R0|Data_out[0]~reg0 ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.757 ns                ;
; N/A   ; 336.59 MHz ( period = 2.971 ns )               ; ROM:R0|Data_out[0]~reg0 ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.756 ns                ;
; N/A   ; 336.93 MHz ( period = 2.968 ns )               ; ROM:R0|Data_out[1]~reg0 ; EA.S0                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.270 ns                ;
; N/A   ; 339.21 MHz ( period = 2.948 ns )               ; ROM:R0|Data_out[0]~reg0 ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.260 ns                ;
; N/A   ; 342.23 MHz ( period = 2.922 ns )               ; EA.S2                   ; endereco[3]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.249 ns                ;
; N/A   ; 342.47 MHz ( period = 2.920 ns )               ; EA.S2                   ; endereco[1]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.248 ns                ;
; N/A   ; 345.18 MHz ( period = 2.897 ns )               ; endereco[0]             ; endereco[4]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.683 ns                ;
; N/A   ; 348.92 MHz ( period = 2.866 ns )               ; ROM:R0|Data_out[2]~reg0 ; EA.S0                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.219 ns                ;
; N/A   ; 353.36 MHz ( period = 2.830 ns )               ; EA.S2                   ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.200 ns                ;
; N/A   ; 354.36 MHz ( period = 2.822 ns )               ; EA.S2                   ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.196 ns                ;
; N/A   ; 358.04 MHz ( period = 2.793 ns )               ; ROM:R0|Data_out[2]~reg0 ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.578 ns                ;
; N/A   ; 358.17 MHz ( period = 2.792 ns )               ; ROM:R0|Data_out[2]~reg0 ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.577 ns                ;
; N/A   ; 364.96 MHz ( period = 2.740 ns )               ; EA.S2                   ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.155 ns                ;
; N/A   ; 367.11 MHz ( period = 2.724 ns )               ; ROM:R0|Data_out[3]~reg0 ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.509 ns                ;
; N/A   ; 367.24 MHz ( period = 2.723 ns )               ; ROM:R0|Data_out[3]~reg0 ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.508 ns                ;
; N/A   ; 368.46 MHz ( period = 2.714 ns )               ; endereco[0]             ; endereco[3]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.503 ns                ;
; N/A   ; 372.72 MHz ( period = 2.683 ns )               ; maior[3]                ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.469 ns                ;
; N/A   ; 372.86 MHz ( period = 2.682 ns )               ; maior[3]                ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.468 ns                ;
; N/A   ; 379.65 MHz ( period = 2.634 ns )               ; EA.S2                   ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.102 ns                ;
; N/A   ; 379.79 MHz ( period = 2.633 ns )               ; maior[4]                ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.419 ns                ;
; N/A   ; 379.94 MHz ( period = 2.632 ns )               ; maior[4]                ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.418 ns                ;
; N/A   ; 380.81 MHz ( period = 2.626 ns )               ; EA.S1                   ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.098 ns                ;
; N/A   ; 380.81 MHz ( period = 2.626 ns )               ; EA.S1                   ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.098 ns                ;
; N/A   ; 381.10 MHz ( period = 2.624 ns )               ; EA.S1                   ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.097 ns                ;
; N/A   ; 381.10 MHz ( period = 2.624 ns )               ; EA.S1                   ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.097 ns                ;
; N/A   ; 381.10 MHz ( period = 2.624 ns )               ; maior[1]                ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.410 ns                ;
; N/A   ; 381.24 MHz ( period = 2.623 ns )               ; maior[1]                ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.409 ns                ;
; N/A   ; 381.39 MHz ( period = 2.622 ns )               ; EA.S1                   ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.096 ns                ;
; N/A   ; 381.97 MHz ( period = 2.618 ns )               ; EA.S1                   ; endereco[4]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.094 ns                ;
; N/A   ; 382.85 MHz ( period = 2.612 ns )               ; EA.S1                   ; endereco[0]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.091 ns                ;
; N/A   ; 383.73 MHz ( period = 2.606 ns )               ; EA.S1                   ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.088 ns                ;
; N/A   ; 383.88 MHz ( period = 2.605 ns )               ; maior[5]                ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.391 ns                ;
; N/A   ; 384.47 MHz ( period = 2.601 ns )               ; maior[5]                ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.387 ns                ;
; N/A   ; 388.50 MHz ( period = 2.574 ns )               ; endereco[0]             ; endereco[1]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.363 ns                ;
; N/A   ; 390.17 MHz ( period = 2.563 ns )               ; ROM:R0|Data_out[4]~reg0 ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.348 ns                ;
; N/A   ; 390.32 MHz ( period = 2.562 ns )               ; ROM:R0|Data_out[4]~reg0 ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.347 ns                ;
; N/A   ; 390.32 MHz ( period = 2.562 ns )               ; ROM:R0|Data_out[7]~reg0 ; maior[1]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.347 ns                ;
; N/A   ; 390.47 MHz ( period = 2.561 ns )               ; maior[2]                ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.347 ns                ;
; N/A   ; 390.63 MHz ( period = 2.560 ns )               ; maior[2]                ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.346 ns                ;
; N/A   ; 390.93 MHz ( period = 2.558 ns )               ; ROM:R0|Data_out[7]~reg0 ; maior[4]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.343 ns                ;
; N/A   ; 392.46 MHz ( period = 2.548 ns )               ; maior[5]                ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.334 ns                ;
; N/A   ; 399.20 MHz ( period = 2.505 ns )               ; ROM:R0|Data_out[7]~reg0 ; maior[5]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.290 ns                ;
; N/A   ; 399.36 MHz ( period = 2.504 ns )               ; EA.S2                   ; endereco[2]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.040 ns                ;
; N/A   ; 401.77 MHz ( period = 2.489 ns )               ; maior[5]                ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.275 ns                ;
; N/A   ; 404.53 MHz ( period = 2.472 ns )               ; EA.S1                   ; endereco[2]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.024 ns                ;
; N/A   ; 408.83 MHz ( period = 2.446 ns )               ; ROM:R0|Data_out[7]~reg0 ; maior[0]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.231 ns                ;
; N/A   ; 415.45 MHz ( period = 2.407 ns )               ; endereco[1]             ; endereco[4]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.190 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; endereco[4]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.153 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; endereco[2]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.122 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; ROM:R0|Data_out[0]~reg0 ; EA.S0                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.950 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; endereco[0]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.106 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; endereco[4]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.043 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; endereco[3]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 2.010 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; endereco[3]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.973 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; maior[5]                ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.788 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; maior[5]                ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.787 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[4]             ; endereco[4]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.748 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; ROM:R0|Data_out[7]~reg0 ; maior[2]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.744 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; ROM:R0|Data_out[7]~reg0 ; maior[3]                ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.743 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; EA.S2                   ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.737 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; EA.S1                   ; endereco[1]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.751 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; ROM:R0|Data_out[7]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.712 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; EA.S1                   ; endereco[3]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.749 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; ROM:R0|Data_out[1]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.686 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; ROM:R0|Data_out[2]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.685 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; endereco[2]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.629 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; ROM:R0|Data_out[3]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.595 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; ROM:R0|Data_out[4]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.594 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; ROM:R0|Data_out[1]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.568 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; endereco[1]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.558 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; ROM:R0|Data_out[7]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.555 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; endereco[3]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.551 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[0]             ; ROM:R0|Data_out[0]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.549 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; ROM:R0|Data_out[2]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.533 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; ROM:R0|Data_out[1]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.531 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; ROM:R0|Data_out[7]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.528 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; ROM:R0|Data_out[2]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.523 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; ROM:R0|Data_out[4]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.466 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; ROM:R0|Data_out[3]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.465 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; ROM:R0|Data_out[3]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.438 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; ROM:R0|Data_out[0]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.426 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; ROM:R0|Data_out[4]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.411 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; ROM:R0|Data_out[7]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; ROM:R0|Data_out[1]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.393 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; ROM:R0|Data_out[2]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.381 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[3]             ; ROM:R0|Data_out[0]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.361 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; EA.S2                   ; EA.S0                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.339 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; ROM:R0|Data_out[4]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.290 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; ROM:R0|Data_out[3]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.290 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[2]             ; endereco[2]             ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.277 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[1]             ; ROM:R0|Data_out[0]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.250 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[4]             ; ROM:R0|Data_out[3]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.092 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[4]             ; ROM:R0|Data_out[7]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.089 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[4]             ; ROM:R0|Data_out[4]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.089 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[4]             ; ROM:R0|Data_out[0]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.088 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[4]             ; ROM:R0|Data_out[1]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.088 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; endereco[4]             ; ROM:R0|Data_out[2]~reg0 ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.088 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; EA.S1                   ; EA.S2                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.861 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; EA.S0                   ; EA.S1                   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.675 ns                ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------+
; tsu                                                           ;
+-------+--------------+------------+--------+-------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To    ; To Clock ;
+-------+--------------+------------+--------+-------+----------+
; N/A   ; None         ; 3.530 ns   ; KEY[0] ; EA.S0 ; CLOCK_50 ;
; N/A   ; None         ; 3.529 ns   ; KEY[0] ; EA.S1 ; CLOCK_50 ;
; N/A   ; None         ; 3.358 ns   ; KEY[0] ; EA.S2 ; CLOCK_50 ;
+-------+--------------+------------+--------+-------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+----------+----------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To       ; From Clock ;
+-------+--------------+------------+----------+----------+------------+
; N/A   ; None         ; 9.272 ns   ; maior[5] ; saida[5] ; CLOCK_50   ;
; N/A   ; None         ; 9.119 ns   ; maior[5] ; saida[6] ; CLOCK_50   ;
; N/A   ; None         ; 8.633 ns   ; maior[5] ; saida[7] ; CLOCK_50   ;
; N/A   ; None         ; 7.894 ns   ; maior[0] ; saida[0] ; CLOCK_50   ;
; N/A   ; None         ; 6.443 ns   ; maior[4] ; saida[4] ; CLOCK_50   ;
; N/A   ; None         ; 6.432 ns   ; maior[2] ; saida[2] ; CLOCK_50   ;
; N/A   ; None         ; 6.418 ns   ; maior[3] ; saida[3] ; CLOCK_50   ;
; N/A   ; None         ; 6.416 ns   ; maior[1] ; saida[1] ; CLOCK_50   ;
+-------+--------------+------------+----------+----------+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+--------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To    ; To Clock ;
+---------------+-------------+-----------+--------+-------+----------+
; N/A           ; None        ; -3.128 ns ; KEY[0] ; EA.S2 ; CLOCK_50 ;
; N/A           ; None        ; -3.299 ns ; KEY[0] ; EA.S1 ; CLOCK_50 ;
; N/A           ; None        ; -3.300 ns ; KEY[0] ; EA.S0 ; CLOCK_50 ;
+---------------+-------------+-----------+--------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.1 Build 222 10/21/2009 SJ Web Edition
    Info: Processing started: Mon Jun 20 21:11:15 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off top -c top --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK_50" is an undefined clock
Info: Clock "CLOCK_50" has Internal fmax of 247.4 MHz between source register "ROM:R0|Data_out[4]~reg0" and destination register "EA.S1" (period= 4.042 ns)
    Info: + Longest register to register delay is 1.807 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y32_N15; Fanout = 3; REG Node = 'ROM:R0|Data_out[4]~reg0'
        Info: 2: + IC(0.513 ns) + CELL(0.410 ns) = 0.923 ns; Loc. = LCCOMB_X35_Y32_N2; Fanout = 2; COMB Node = 'Equal0~0'
        Info: 3: + IC(0.254 ns) + CELL(0.150 ns) = 1.327 ns; Loc. = LCCOMB_X35_Y32_N22; Fanout = 1; COMB Node = 'EA~10'
        Info: 4: + IC(0.246 ns) + CELL(0.150 ns) = 1.723 ns; Loc. = LCCOMB_X35_Y32_N24; Fanout = 1; COMB Node = 'EA~8'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.807 ns; Loc. = LCFF_X35_Y32_N25; Fanout = 12; REG Node = 'EA.S1'
        Info: Total cell delay = 0.794 ns ( 43.94 % )
        Info: Total interconnect delay = 1.013 ns ( 56.06 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLOCK_50" to destination register is 2.664 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK_50'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'CLOCK_50~clkctrl'
            Info: 3: + IC(1.010 ns) + CELL(0.537 ns) = 2.664 ns; Loc. = LCFF_X35_Y32_N25; Fanout = 12; REG Node = 'EA.S1'
            Info: Total cell delay = 1.536 ns ( 57.66 % )
            Info: Total interconnect delay = 1.128 ns ( 42.34 % )
        Info: - Longest clock path from clock "CLOCK_50" to source register is 2.664 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK_50'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'CLOCK_50~clkctrl'
            Info: 3: + IC(1.010 ns) + CELL(0.537 ns) = 2.664 ns; Loc. = LCFF_X35_Y32_N15; Fanout = 3; REG Node = 'ROM:R0|Data_out[4]~reg0'
            Info: Total cell delay = 1.536 ns ( 57.66 % )
            Info: Total interconnect delay = 1.128 ns ( 42.34 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: tsu for register "EA.S0" (data pin = "KEY[0]", clock pin = "CLOCK_50") is 3.530 ns
    Info: + Longest pin to register delay is 6.230 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_F14; Fanout = 3; PIN Node = 'KEY[0]'
        Info: 2: + IC(4.878 ns) + CELL(0.438 ns) = 6.146 ns; Loc. = LCCOMB_X35_Y32_N8; Fanout = 1; COMB Node = 'EA~9'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.230 ns; Loc. = LCFF_X35_Y32_N9; Fanout = 1; REG Node = 'EA.S0'
        Info: Total cell delay = 1.352 ns ( 21.70 % )
        Info: Total interconnect delay = 4.878 ns ( 78.30 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "CLOCK_50" to destination register is 2.664 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK_50'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'CLOCK_50~clkctrl'
        Info: 3: + IC(1.010 ns) + CELL(0.537 ns) = 2.664 ns; Loc. = LCFF_X35_Y32_N9; Fanout = 1; REG Node = 'EA.S0'
        Info: Total cell delay = 1.536 ns ( 57.66 % )
        Info: Total interconnect delay = 1.128 ns ( 42.34 % )
Info: tco from clock "CLOCK_50" to destination pin "saida[5]" through register "maior[5]" is 9.272 ns
    Info: + Longest clock path from clock "CLOCK_50" to source register is 2.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK_50'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'CLOCK_50~clkctrl'
        Info: 3: + IC(1.009 ns) + CELL(0.537 ns) = 2.663 ns; Loc. = LCFF_X34_Y32_N27; Fanout = 6; REG Node = 'maior[5]'
        Info: Total cell delay = 1.536 ns ( 57.68 % )
        Info: Total interconnect delay = 1.127 ns ( 42.32 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 6.359 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y32_N27; Fanout = 6; REG Node = 'maior[5]'
        Info: 2: + IC(3.561 ns) + CELL(2.798 ns) = 6.359 ns; Loc. = PIN_AE13; Fanout = 0; PIN Node = 'saida[5]'
        Info: Total cell delay = 2.798 ns ( 44.00 % )
        Info: Total interconnect delay = 3.561 ns ( 56.00 % )
Info: th for register "EA.S2" (data pin = "KEY[0]", clock pin = "CLOCK_50") is -3.128 ns
    Info: + Longest clock path from clock "CLOCK_50" to destination register is 2.664 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'CLOCK_50'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 20; COMB Node = 'CLOCK_50~clkctrl'
        Info: 3: + IC(1.010 ns) + CELL(0.537 ns) = 2.664 ns; Loc. = LCFF_X35_Y32_N1; Fanout = 13; REG Node = 'EA.S2'
        Info: Total cell delay = 1.536 ns ( 57.66 % )
        Info: Total interconnect delay = 1.128 ns ( 42.34 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 6.058 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_F14; Fanout = 3; PIN Node = 'KEY[0]'
        Info: 2: + IC(4.869 ns) + CELL(0.275 ns) = 5.974 ns; Loc. = LCCOMB_X35_Y32_N0; Fanout = 1; COMB Node = 'EA~7'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.058 ns; Loc. = LCFF_X35_Y32_N1; Fanout = 13; REG Node = 'EA.S2'
        Info: Total cell delay = 1.189 ns ( 19.63 % )
        Info: Total interconnect delay = 4.869 ns ( 80.37 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 174 megabytes
    Info: Processing ended: Mon Jun 20 21:11:16 2011
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


