TimeQuest Timing Analyzer report for top
Sun Aug 04 20:00:33 2013
Quartus II 32-bit Version 12.1 Build 177 11/07/2012 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow Model Fmax Summary
  6. Slow Model Setup Summary
  7. Slow Model Hold Summary
  8. Slow Model Recovery Summary
  9. Slow Model Removal Summary
 10. Slow Model Minimum Pulse Width Summary
 11. Slow Model Setup: 'CLOCK_50'
 12. Slow Model Hold: 'CLOCK_50'
 13. Slow Model Minimum Pulse Width: 'CLOCK_50'
 14. Setup Times
 15. Hold Times
 16. Clock to Output Times
 17. Minimum Clock to Output Times
 18. Fast Model Setup Summary
 19. Fast Model Hold Summary
 20. Fast Model Recovery Summary
 21. Fast Model Removal Summary
 22. Fast Model Minimum Pulse Width Summary
 23. Fast Model Setup: 'CLOCK_50'
 24. Fast Model Hold: 'CLOCK_50'
 25. Fast Model Minimum Pulse Width: 'CLOCK_50'
 26. Setup Times
 27. Hold Times
 28. Clock to Output Times
 29. Minimum Clock to Output Times
 30. Multicorner Timing Analysis Summary
 31. Setup Times
 32. Hold Times
 33. Clock to Output Times
 34. Minimum Clock to Output Times
 35. Setup Transfers
 36. Hold Transfers
 37. Report TCCS
 38. Report RSKM
 39. Unconstrained Paths
 40. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                     ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 12.1 Build 177 11/07/2012 SJ Web Edition ;
; Revision Name      ; top                                              ;
; Device Family      ; Cyclone II                                       ;
; Device Name        ; EP2C35F672C6                                     ;
; Timing Models      ; Final                                            ;
; Delay Model        ; Combined                                         ;
; Rise/Fall Delays   ; Unavailable                                      ;
+--------------------+--------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ; < 0.1%      ;
;     3-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                               ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets      ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
; CLOCK_50   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+


+--------------------------------------------------+
; Slow Model Fmax Summary                          ;
+------------+-----------------+------------+------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+------+
; 151.47 MHz ; 151.47 MHz      ; CLOCK_50   ;      ;
+------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+-----------------------------------+
; Slow Model Setup Summary          ;
+----------+--------+---------------+
; Clock    ; Slack  ; End Point TNS ;
+----------+--------+---------------+
; CLOCK_50 ; -5.602 ; -66.592       ;
+----------+--------+---------------+


+----------------------------------+
; Slow Model Hold Summary          ;
+----------+-------+---------------+
; Clock    ; Slack ; End Point TNS ;
+----------+-------+---------------+
; CLOCK_50 ; 0.391 ; 0.000         ;
+----------+-------+---------------+


-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.


------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.


+----------------------------------------+
; Slow Model Minimum Pulse Width Summary ;
+----------+--------+--------------------+
; Clock    ; Slack  ; End Point TNS      ;
+----------+--------+--------------------+
; CLOCK_50 ; -1.627 ; -94.460            ;
+----------+--------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLOCK_50'                                                                                                                                                         ;
+--------+--------------------------------------------------------------------------------------------+----------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                  ; To Node  ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------+----------+--------------+-------------+--------------+------------+------------+
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.602 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.553      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.486 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.437      ;
; -5.485 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.436      ;
; -5.485 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.436      ;
; -5.485 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.436      ;
; -5.485 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.436      ;
; -5.485 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.085     ; 6.436      ;
; -4.308 ; endereco[4]                                                                                ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.343      ;
; -4.308 ; endereco[4]                                                                                ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.343      ;
; -4.192 ; endereco[4]                                                                                ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.227      ;
; -4.192 ; endereco[4]                                                                                ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.227      ;
; -4.191 ; endereco[4]                                                                                ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.226      ;
; -4.015 ; endereco[1]                                                                                ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.050      ;
; -4.015 ; endereco[1]                                                                                ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.050      ;
; -3.987 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.022      ;
; -3.987 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 5.022      ;
; -3.899 ; endereco[1]                                                                                ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.934      ;
; -3.899 ; endereco[1]                                                                                ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.934      ;
; -3.898 ; endereco[1]                                                                                ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.933      ;
; -3.871 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.906      ;
; -3.871 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.906      ;
; -3.870 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.905      ;
; -3.864 ; maior[3]                                                                                   ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.900      ;
; -3.860 ; maior[3]                                                                                   ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.896      ;
; -3.844 ; endereco[3]                                                                                ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.884      ;
; -3.844 ; endereco[3]                                                                                ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.884      ;
; -3.814 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.854      ;
; -3.810 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.850      ;
; -3.804 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.844      ;
; -3.804 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.844      ;
; -3.738 ; maior[3]                                                                                   ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.774      ;
; -3.738 ; maior[3]                                                                                   ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.774      ;
; -3.737 ; maior[3]                                                                                   ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.773      ;
; -3.737 ; endereco[0]                                                                                ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.772      ;
; -3.737 ; endereco[0]                                                                                ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.772      ;
; -3.728 ; endereco[3]                                                                                ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.768      ;
; -3.728 ; endereco[3]                                                                                ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.768      ;
; -3.727 ; endereco[3]                                                                                ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.767      ;
; -3.688 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.728      ;
; -3.688 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.728      ;
; -3.688 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.728      ;
; -3.688 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.728      ;
; -3.687 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.727      ;
; -3.687 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.727      ;
; -3.621 ; endereco[0]                                                                                ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.656      ;
; -3.621 ; endereco[0]                                                                                ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.656      ;
; -3.620 ; endereco[0]                                                                                ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.655      ;
; -3.570 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.605      ;
; -3.570 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.605      ;
; -3.549 ; maior[4]                                                                                   ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.585      ;
; -3.546 ; endereco[2]                                                                                ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.586      ;
; -3.546 ; endereco[2]                                                                                ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.586      ;
; -3.545 ; maior[4]                                                                                   ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.581      ;
; -3.538 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.578      ;
; -3.538 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.578      ;
; -3.454 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.489      ;
; -3.454 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.489      ;
; -3.453 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 4.488      ;
; -3.430 ; endereco[2]                                                                                ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.470      ;
; -3.430 ; endereco[2]                                                                                ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.470      ;
; -3.429 ; endereco[2]                                                                                ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.469      ;
; -3.423 ; maior[4]                                                                                   ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.459      ;
; -3.423 ; maior[4]                                                                                   ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.459      ;
; -3.422 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.462      ;
; -3.422 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.462      ;
; -3.422 ; maior[4]                                                                                   ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.458      ;
; -3.421 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.461      ;
; -3.410 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.450      ;
; -3.410 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.450      ;
; -3.385 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.425      ;
; -3.385 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.425      ;
; -3.294 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.334      ;
; -3.294 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.334      ;
; -3.293 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.333      ;
; -3.269 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.309      ;
; -3.269 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.309      ;
; -3.268 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 4.308      ;
; -3.168 ; maior[2]                                                                                   ; maior[0] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.204      ;
; -3.164 ; maior[2]                                                                                   ; maior[1] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.200      ;
; -3.042 ; maior[2]                                                                                   ; maior[4] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.078      ;
; -3.042 ; maior[2]                                                                                   ; maior[3] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.078      ;
; -3.041 ; maior[2]                                                                                   ; maior[2] ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 4.077      ;
+--------+--------------------------------------------------------------------------------------------+----------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLOCK_50'                                                                                                                                                                            ;
+-------+-----------------------------+--------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+--------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.391 ; endereco[4]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; maior[2]                    ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; maior[1]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; maior[4]                    ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; maior[3]                    ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; maior[0]                    ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; EA.S1                       ; EA.S1                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.657      ;
; 0.532 ; EA.S1                       ; EA.S2                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.798      ;
; 0.552 ; endereco[2]                 ; dt_in[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.818      ;
; 0.559 ; endereco[0]                 ; dt_in[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.825      ;
; 0.640 ; dt_in[4]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg4  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.934      ;
; 0.643 ; dt_in[3]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg3  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.937      ;
; 0.648 ; dt_in[2]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg2  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.942      ;
; 0.678 ; dt_in[4]                    ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.944      ;
; 0.680 ; endereco[3]                 ; dt_in[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.946      ;
; 0.681 ; endereco[3]                 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.947      ;
; 0.831 ; endereco[2]                 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.097      ;
; 0.850 ; dt_in[2]                    ; RAM:R0|mem_rtl_0_bypass[13]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.116      ;
; 0.852 ; dt_in[1]                    ; RAM:R0|mem_rtl_0_bypass[12]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.118      ;
; 0.858 ; endereco[0]                 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.124      ;
; 0.900 ; dt_in[0]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg0  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.189      ;
; 0.906 ; dt_in[1]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg1  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 1.195      ;
; 0.942 ; endereco[3]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg3 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.237      ;
; 0.951 ; endereco[2]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg2 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.246      ;
; 0.966 ; endereco[1]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg1 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.256      ;
; 1.030 ; endereco[0]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.320      ;
; 1.066 ; dt_in[3]                    ; RAM:R0|mem_rtl_0_bypass[14]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.332      ;
; 1.081 ; dt_in[0]                    ; RAM:R0|mem_rtl_0_bypass[11]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.001     ; 1.346      ;
; 1.097 ; endereco[1]                 ; dt_in[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.363      ;
; 1.100 ; endereco[1]                 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.366      ;
; 1.181 ; endereco[4]                 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.005     ; 1.442      ;
; 1.183 ; endereco[4]                 ; dt_in[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.005     ; 1.444      ;
; 1.231 ; EA.S1                       ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.997      ;
; 1.240 ; endereco[0]                 ; endereco[0]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.506      ;
; 1.242 ; endereco[4]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.084      ; 1.560      ;
; 1.490 ; endereco[1]                 ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.756      ;
; 1.535 ; endereco[4]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 1.825      ;
; 1.535 ; EA.S2                       ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 1.301      ;
; 1.610 ; endereco[0]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.084      ; 1.928      ;
; 1.634 ; EA.S1                       ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 1.400      ;
; 1.640 ; EA.S1                       ; endereco[0]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 1.406      ;
; 1.647 ; EA.S1                       ; dt_in[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 1.413      ;
; 1.647 ; EA.S1                       ; dt_in[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 1.413      ;
; 1.783 ; EA.S1                       ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.548      ;
; 1.784 ; EA.S1                       ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.549      ;
; 1.801 ; EA.S2                       ; endereco[0]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 1.567      ;
; 1.823 ; EA.S1                       ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.588      ;
; 1.824 ; EA.S1                       ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.589      ;
; 1.824 ; EA.S1                       ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.589      ;
; 1.876 ; endereco[1]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.084      ; 2.194      ;
; 1.935 ; EA.S2                       ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 1.701      ;
; 2.010 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 1.828      ;
; 2.018 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 1.836      ;
; 2.020 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 1.838      ;
; 2.057 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 1.875      ;
; 2.067 ; endereco[3]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.089      ; 2.390      ;
; 2.074 ; endereco[1]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.340      ;
; 2.082 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 1.900      ;
; 2.086 ; endereco[2]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.089      ; 2.409      ;
; 2.090 ; EA.S1                       ; endereco[3]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.005     ; 1.851      ;
; 2.102 ; EA.S1                       ; endereco[2]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.005     ; 1.863      ;
; 2.126 ; EA.S1                       ; dt_in[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.005     ; 1.887      ;
; 2.126 ; EA.S1                       ; dt_in[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.005     ; 1.887      ;
; 2.126 ; EA.S1                       ; dt_in[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.005     ; 1.887      ;
; 2.131 ; endereco[2]                 ; endereco[2]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.397      ;
; 2.132 ; endereco[0]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.398      ;
; 2.139 ; endereco[3]                 ; endereco[3]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.405      ;
; 2.147 ; EA.S2                       ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.912      ;
; 2.160 ; RAM:R0|mem_rtl_0_bypass[11] ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.426      ;
; 2.171 ; EA.S2                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 1.989      ;
; 2.179 ; EA.S2                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 1.997      ;
; 2.198 ; EA.S2                       ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.963      ;
; 2.203 ; EA.S2                       ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 1.968      ;
; 2.217 ; EA.S2                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 2.035      ;
; 2.251 ; EA.S2                       ; endereco[3]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.005     ; 2.012      ;
; 2.262 ; EA.S2                       ; endereco[2]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.005     ; 2.023      ;
; 2.316 ; maior[2]                    ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.582      ;
; 2.319 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 2.589      ;
; 2.319 ; maior[2]                    ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.585      ;
; 2.320 ; RAM:R0|mem_rtl_0_bypass[12] ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.001     ; 2.585      ;
; 2.321 ; EA.S2                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 2.139      ;
; 2.325 ; RAM:R0|mem_rtl_0_bypass[14] ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 2.595      ;
; 2.349 ; EA.S2                       ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 2.114      ;
; 2.349 ; EA.S2                       ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 2.114      ;
; 2.369 ; endereco[3]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 2.640      ;
; 2.369 ; maior[4]                    ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.635      ;
; 2.376 ; maior[4]                    ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.642      ;
; 2.386 ; EA.S2                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.084      ; 2.204      ;
; 2.390 ; maior[3]                    ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.656      ;
; 2.400 ; maior[3]                    ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.666      ;
; 2.419 ; endereco[2]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 2.690      ;
; 2.496 ; endereco[0]                 ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.762      ;
; 2.512 ; maior[2]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.778      ;
; 2.512 ; maior[2]                    ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.778      ;
; 2.558 ; RAM:R0|mem_rtl_0_bypass[15] ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 2.828      ;
; 2.562 ; maior[4]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.828      ;
; 2.562 ; maior[4]                    ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.828      ;
; 2.574 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 2.844      ;
; 2.580 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 2.850      ;
; 2.586 ; maior[3]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 2.852      ;
+-------+-----------------------------+--------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLOCK_50'                                                                                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------+
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg1  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg1  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg2  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg2  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg3  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg3  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg4  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg4  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a1~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a1~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a2~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a2~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a3~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a3~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a4~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a4~porta_memory_reg0  ;
; -1.380 ; 1.000        ; 2.380          ; Port Rate        ; CLOCK_50 ; Rise       ; CLOCK_50                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Fall       ; EA.S1                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Fall       ; EA.S1                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Fall       ; EA.S2                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Fall       ; EA.S2                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[11]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[11]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[12]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[12]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[13]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[13]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[14]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[14]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[15]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[15]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[4]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[4]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[0]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[0]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[1]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[1]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[2]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[2]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[3]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[3]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[4]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[4]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[4]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[4]                                                                                   ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                                                           ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                                                           ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~clkctrl|inclk[0]                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; KEY[*]    ; CLOCK_50   ; 3.848 ; 3.848 ; Fall       ; CLOCK_50        ;
;  KEY[0]   ; CLOCK_50   ; 3.848 ; 3.848 ; Fall       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; KEY[*]    ; CLOCK_50   ; -3.371 ; -3.371 ; Fall       ; CLOCK_50        ;
;  KEY[0]   ; CLOCK_50   ; -3.371 ; -3.371 ; Fall       ; CLOCK_50        ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; saida[*]  ; CLOCK_50   ; 7.555 ; 7.555 ; Rise       ; CLOCK_50        ;
;  saida[0] ; CLOCK_50   ; 7.318 ; 7.318 ; Rise       ; CLOCK_50        ;
;  saida[1] ; CLOCK_50   ; 7.364 ; 7.364 ; Rise       ; CLOCK_50        ;
;  saida[2] ; CLOCK_50   ; 7.516 ; 7.516 ; Rise       ; CLOCK_50        ;
;  saida[3] ; CLOCK_50   ; 7.555 ; 7.555 ; Rise       ; CLOCK_50        ;
;  saida[4] ; CLOCK_50   ; 7.278 ; 7.278 ; Rise       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; saida[*]  ; CLOCK_50   ; 7.278 ; 7.278 ; Rise       ; CLOCK_50        ;
;  saida[0] ; CLOCK_50   ; 7.318 ; 7.318 ; Rise       ; CLOCK_50        ;
;  saida[1] ; CLOCK_50   ; 7.364 ; 7.364 ; Rise       ; CLOCK_50        ;
;  saida[2] ; CLOCK_50   ; 7.516 ; 7.516 ; Rise       ; CLOCK_50        ;
;  saida[3] ; CLOCK_50   ; 7.555 ; 7.555 ; Rise       ; CLOCK_50        ;
;  saida[4] ; CLOCK_50   ; 7.278 ; 7.278 ; Rise       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------+
; Fast Model Setup Summary          ;
+----------+--------+---------------+
; Clock    ; Slack  ; End Point TNS ;
+----------+--------+---------------+
; CLOCK_50 ; -2.549 ; -25.443       ;
+----------+--------+---------------+


+----------------------------------+
; Fast Model Hold Summary          ;
+----------+-------+---------------+
; Clock    ; Slack ; End Point TNS ;
+----------+-------+---------------+
; CLOCK_50 ; 0.215 ; 0.000         ;
+----------+-------+---------------+


-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.


------------------------------
; Fast Model Removal Summary ;
------------------------------
No paths to report.


+----------------------------------------+
; Fast Model Minimum Pulse Width Summary ;
+----------+--------+--------------------+
; Clock    ; Slack  ; End Point TNS      ;
+----------+--------+--------------------+
; CLOCK_50 ; -1.627 ; -94.460            ;
+----------+--------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CLOCK_50'                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                  ; To Node                                                                                   ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -2.549 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.516      ;
; -2.549 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.516      ;
; -2.549 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.516      ;
; -2.549 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.516      ;
; -2.549 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.516      ;
; -2.546 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.513      ;
; -2.546 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.513      ;
; -2.546 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.513      ;
; -2.546 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.513      ;
; -2.546 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.065     ; 3.513      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -2.510 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.066     ; 3.476      ;
; -1.460 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg0  ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_memory_reg0 ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.017     ; 2.442      ;
; -1.460 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg1  ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a1~porta_memory_reg0 ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.017     ; 2.442      ;
; -1.460 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg2  ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a2~porta_memory_reg0 ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.017     ; 2.442      ;
; -1.460 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg3  ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a3~porta_memory_reg0 ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.017     ; 2.442      ;
; -1.460 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg4  ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a4~porta_memory_reg0 ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.017     ; 2.442      ;
; -1.395 ; endereco[4]                                                                                ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.427      ;
; -1.392 ; endereco[4]                                                                                ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.424      ;
; -1.356 ; endereco[4]                                                                                ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.387      ;
; -1.356 ; endereco[4]                                                                                ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.387      ;
; -1.356 ; endereco[4]                                                                                ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.387      ;
; -1.223 ; endereco[1]                                                                                ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.255      ;
; -1.220 ; endereco[1]                                                                                ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.252      ;
; -1.217 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.249      ;
; -1.214 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.246      ;
; -1.184 ; endereco[1]                                                                                ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.215      ;
; -1.184 ; endereco[1]                                                                                ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.215      ;
; -1.184 ; endereco[1]                                                                                ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.215      ;
; -1.178 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.209      ;
; -1.178 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.209      ;
; -1.178 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.209      ;
; -1.143 ; maior[3]                                                                                   ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.001      ; 2.176      ;
; -1.143 ; endereco[3]                                                                                ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.180      ;
; -1.141 ; maior[3]                                                                                   ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.001      ; 2.174      ;
; -1.140 ; endereco[3]                                                                                ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.177      ;
; -1.126 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.163      ;
; -1.123 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.160      ;
; -1.123 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.160      ;
; -1.121 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.158      ;
; -1.110 ; endereco[0]                                                                                ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.142      ;
; -1.107 ; endereco[0]                                                                                ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.139      ;
; -1.104 ; endereco[3]                                                                                ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.140      ;
; -1.104 ; endereco[3]                                                                                ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.140      ;
; -1.104 ; endereco[3]                                                                                ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.140      ;
; -1.095 ; maior[3]                                                                                   ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.127      ;
; -1.095 ; maior[3]                                                                                   ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.127      ;
; -1.095 ; maior[3]                                                                                   ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.127      ;
; -1.087 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.123      ;
; -1.087 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.123      ;
; -1.087 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.123      ;
; -1.075 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.111      ;
; -1.075 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.111      ;
; -1.075 ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.111      ;
; -1.071 ; endereco[0]                                                                                ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.102      ;
; -1.071 ; endereco[0]                                                                                ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.102      ;
; -1.071 ; endereco[0]                                                                                ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.102      ;
; -1.067 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.099      ;
; -1.064 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 2.096      ;
; -1.028 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.059      ;
; -1.028 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.059      ;
; -1.028 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; -0.001     ; 2.059      ;
; -1.015 ; endereco[2]                                                                                ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.052      ;
; -1.012 ; endereco[2]                                                                                ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.049      ;
; -1.008 ; maior[4]                                                                                   ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.001      ; 2.041      ;
; -1.006 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.043      ;
; -1.006 ; maior[4]                                                                                   ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.001      ; 2.039      ;
; -1.003 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.040      ;
; -0.983 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.020      ;
; -0.980 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.017      ;
; -0.976 ; endereco[2]                                                                                ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.012      ;
; -0.976 ; endereco[2]                                                                                ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.012      ;
; -0.976 ; endereco[2]                                                                                ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.012      ;
; -0.975 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[1]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.012      ;
; -0.972 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[0]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.005      ; 2.009      ;
; -0.967 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.003      ;
; -0.967 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.003      ;
; -0.967 ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 2.003      ;
; -0.960 ; maior[4]                                                                                   ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 1.992      ;
; -0.960 ; maior[4]                                                                                   ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 1.992      ;
; -0.960 ; maior[4]                                                                                   ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.000      ; 1.992      ;
; -0.944 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 1.980      ;
; -0.944 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 1.980      ;
; -0.944 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 1.980      ;
; -0.936 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[2]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 1.972      ;
; -0.936 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[4]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 1.972      ;
; -0.936 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; maior[3]                                                                                  ; CLOCK_50     ; CLOCK_50    ; 1.000        ; 0.004      ; 1.972      ;
+--------+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CLOCK_50'                                                                                                                                                                            ;
+-------+-----------------------------+--------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                   ; To Node                                                                                    ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------+--------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.215 ; endereco[4]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; maior[2]                    ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; maior[1]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; maior[4]                    ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; maior[3]                    ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; maior[0]                    ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; EA.S1                       ; EA.S1                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.367      ;
; 0.242 ; EA.S1                       ; EA.S2                                                                                      ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.394      ;
; 0.252 ; dt_in[4]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg4  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 0.455      ;
; 0.255 ; endereco[2]                 ; dt_in[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.407      ;
; 0.256 ; dt_in[2]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg2  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 0.459      ;
; 0.257 ; dt_in[3]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg3  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 0.460      ;
; 0.260 ; endereco[0]                 ; dt_in[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.412      ;
; 0.335 ; endereco[3]                 ; dt_in[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.487      ;
; 0.336 ; endereco[3]                 ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.488      ;
; 0.336 ; dt_in[4]                    ; RAM:R0|mem_rtl_0_bypass[15]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.488      ;
; 0.381 ; dt_in[0]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg0  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.579      ;
; 0.384 ; dt_in[1]                    ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg1  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 0.582      ;
; 0.406 ; endereco[3]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg3 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 0.610      ;
; 0.408 ; endereco[2]                 ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.560      ;
; 0.411 ; endereco[2]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg2 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 0.615      ;
; 0.411 ; dt_in[2]                    ; RAM:R0|mem_rtl_0_bypass[13]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.563      ;
; 0.413 ; endereco[0]                 ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.565      ;
; 0.413 ; dt_in[1]                    ; RAM:R0|mem_rtl_0_bypass[12]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.565      ;
; 0.423 ; endereco[1]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg1 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.622      ;
; 0.463 ; endereco[0]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.662      ;
; 0.503 ; dt_in[3]                    ; RAM:R0|mem_rtl_0_bypass[14]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.655      ;
; 0.510 ; dt_in[0]                    ; RAM:R0|mem_rtl_0_bypass[11]                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.662      ;
; 0.520 ; endereco[1]                 ; dt_in[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.672      ;
; 0.524 ; endereco[1]                 ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.676      ;
; 0.551 ; endereco[0]                 ; endereco[0]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.703      ;
; 0.584 ; endereco[4]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 0.787      ;
; 0.594 ; endereco[4]                 ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.005     ; 0.741      ;
; 0.596 ; endereco[4]                 ; dt_in[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.005     ; 0.743      ;
; 0.649 ; endereco[1]                 ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 0.801      ;
; 0.690 ; endereco[4]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg4 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.889      ;
; 0.704 ; endereco[0]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 0.907      ;
; 0.812 ; endereco[1]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 1.015      ;
; 0.847 ; EA.S1                       ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.499      ;
; 0.879 ; endereco[1]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.031      ;
; 0.906 ; endereco[3]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.070      ; 1.114      ;
; 0.912 ; endereco[0]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.064      ;
; 0.924 ; endereco[2]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.070      ; 1.132      ;
; 0.935 ; RAM:R0|mem_rtl_0_bypass[11] ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.087      ;
; 0.957 ; endereco[3]                 ; endereco[3]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.109      ;
; 0.961 ; endereco[2]                 ; endereco[2]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.113      ;
; 0.975 ; EA.S2                       ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.627      ;
; 0.993 ; maior[2]                    ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.145      ;
; 0.997 ; maior[2]                    ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.149      ;
; 1.008 ; endereco[3]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 1.165      ;
; 1.015 ; EA.S1                       ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.667      ;
; 1.016 ; RAM:R0|mem_rtl_0_bypass[12] ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.168      ;
; 1.020 ; EA.S1                       ; endereco[0]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.672      ;
; 1.021 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.177      ;
; 1.024 ; RAM:R0|mem_rtl_0_bypass[14] ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.180      ;
; 1.034 ; maior[4]                    ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.186      ;
; 1.035 ; endereco[2]                 ; endereco[4]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 1.192      ;
; 1.037 ; maior[4]                    ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.189      ;
; 1.051 ; endereco[0]                 ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.203      ;
; 1.062 ; maior[3]                    ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.214      ;
; 1.069 ; maior[3]                    ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.000      ; 1.221      ;
; 1.073 ; EA.S1                       ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.725      ;
; 1.073 ; EA.S1                       ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.725      ;
; 1.073 ; EA.S2                       ; endereco[0]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.725      ;
; 1.077 ; maior[2]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.001      ; 1.230      ;
; 1.077 ; maior[2]                    ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.001      ; 1.230      ;
; 1.111 ; EA.S1                       ; dt_in[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.763      ;
; 1.111 ; EA.S1                       ; dt_in[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.763      ;
; 1.112 ; EA.S1                       ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 0.763      ;
; 1.113 ; EA.S1                       ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 0.764      ;
; 1.113 ; EA.S1                       ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; -0.500       ; -0.001     ; 0.764      ;
; 1.114 ; maior[4]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.001      ; 1.267      ;
; 1.114 ; maior[4]                    ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.001      ; 1.267      ;
; 1.120 ; RAM:R0|mem_rtl_0_bypass[15] ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.276      ;
; 1.125 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.281      ;
; 1.131 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.287      ;
; 1.137 ; RAM:R0|mem_rtl_0_bypass[14] ; maior[4]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.293      ;
; 1.139 ; EA.S2                       ; endereco[1]                                                                                ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.000      ; 0.791      ;
; 1.144 ; RAM:R0|mem_rtl_0_bypass[14] ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.300      ;
; 1.146 ; maior[3]                    ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.001      ; 1.299      ;
; 1.146 ; maior[3]                    ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.001      ; 1.299      ;
; 1.164 ; endereco[1]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 1.367      ;
; 1.165 ; endereco[1]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 1.368      ;
; 1.173 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.065      ; 0.876      ;
; 1.178 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.065      ; 0.881      ;
; 1.179 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.065      ; 0.882      ;
; 1.197 ; endereco[0]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 1.400      ;
; 1.198 ; endereco[0]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 1.401      ;
; 1.201 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.065      ; 0.904      ;
; 1.201 ; endereco[1]                 ; endereco[2]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.005     ; 1.348      ;
; 1.213 ; RAM:R0|mem_rtl_0_bypass[15] ; maior[3]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.369      ;
; 1.214 ; endereco[0]                 ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 1.417      ;
; 1.216 ; EA.S1                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.065      ; 0.919      ;
; 1.216 ; endereco[1]                 ; endereco[3]                                                                                ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.005     ; 1.363      ;
; 1.216 ; RAM:R0|mem_rtl_0_bypass[15] ; maior[2]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.004      ; 1.372      ;
; 1.218 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 1.375      ;
; 1.218 ; RAM:R0|mem_rtl_0_bypass[13] ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 1.375      ;
; 1.221 ; RAM:R0|mem_rtl_0_bypass[14] ; maior[1]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 1.378      ;
; 1.221 ; RAM:R0|mem_rtl_0_bypass[14] ; maior[0]                                                                                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.005      ; 1.378      ;
; 1.226 ; EA.S2                       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ; CLOCK_50     ; CLOCK_50    ; -0.500       ; 0.065      ; 0.929      ;
+-------+-----------------------------+--------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLOCK_50'                                                                                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------+
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg1  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg1  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg2  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg2  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg3  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg3  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg4  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_datain_reg4  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg0 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg1 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg2 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg3 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a0~portb_address_reg4 ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a1~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a1~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a2~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a2~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a3~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a3~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a4~porta_memory_reg0  ;
; -1.627 ; 0.500        ; 2.127          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ram_block1a4~porta_memory_reg0  ;
; -1.380 ; 1.000        ; 2.380          ; Port Rate        ; CLOCK_50 ; Rise       ; CLOCK_50                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Fall       ; EA.S1                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Fall       ; EA.S1                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Fall       ; EA.S2                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Fall       ; EA.S2                                                                                      ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[0]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[11]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[11]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[12]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[12]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[13]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[13]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[14]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[14]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[15]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[15]                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[1]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[3]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[5]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[7]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; RAM:R0|mem_rtl_0_bypass[9]                                                                 ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; dt_in[4]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; dt_in[4]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[0]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[0]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[1]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[1]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[2]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[2]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[3]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[3]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; endereco[4]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; endereco[4]                                                                                ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[0]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[1]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[2]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[3]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; maior[4]                                                                                   ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; maior[4]                                                                                   ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                                                           ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                                                           ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~clkctrl|inclk[0]                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; KEY[*]    ; CLOCK_50   ; 2.067 ; 2.067 ; Fall       ; CLOCK_50        ;
;  KEY[0]   ; CLOCK_50   ; 2.067 ; 2.067 ; Fall       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; KEY[*]    ; CLOCK_50   ; -1.824 ; -1.824 ; Fall       ; CLOCK_50        ;
;  KEY[0]   ; CLOCK_50   ; -1.824 ; -1.824 ; Fall       ; CLOCK_50        ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; saida[*]  ; CLOCK_50   ; 4.200 ; 4.200 ; Rise       ; CLOCK_50        ;
;  saida[0] ; CLOCK_50   ; 4.102 ; 4.102 ; Rise       ; CLOCK_50        ;
;  saida[1] ; CLOCK_50   ; 4.119 ; 4.119 ; Rise       ; CLOCK_50        ;
;  saida[2] ; CLOCK_50   ; 4.187 ; 4.187 ; Rise       ; CLOCK_50        ;
;  saida[3] ; CLOCK_50   ; 4.200 ; 4.200 ; Rise       ; CLOCK_50        ;
;  saida[4] ; CLOCK_50   ; 4.084 ; 4.084 ; Rise       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; saida[*]  ; CLOCK_50   ; 4.084 ; 4.084 ; Rise       ; CLOCK_50        ;
;  saida[0] ; CLOCK_50   ; 4.102 ; 4.102 ; Rise       ; CLOCK_50        ;
;  saida[1] ; CLOCK_50   ; 4.119 ; 4.119 ; Rise       ; CLOCK_50        ;
;  saida[2] ; CLOCK_50   ; 4.187 ; 4.187 ; Rise       ; CLOCK_50        ;
;  saida[3] ; CLOCK_50   ; 4.200 ; 4.200 ; Rise       ; CLOCK_50        ;
;  saida[4] ; CLOCK_50   ; 4.084 ; 4.084 ; Rise       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                           ;
+------------------+---------+-------+----------+---------+---------------------+
; Clock            ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+---------+-------+----------+---------+---------------------+
; Worst-case Slack ; -5.602  ; 0.215 ; N/A      ; N/A     ; -1.627              ;
;  CLOCK_50        ; -5.602  ; 0.215 ; N/A      ; N/A     ; -1.627              ;
; Design-wide TNS  ; -66.592 ; 0.0   ; 0.0      ; 0.0     ; -94.46              ;
;  CLOCK_50        ; -66.592 ; 0.000 ; N/A      ; N/A     ; -94.460             ;
+------------------+---------+-------+----------+---------+---------------------+


+-----------------------------------------------------------------------+
; Setup Times                                                           ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; KEY[*]    ; CLOCK_50   ; 3.848 ; 3.848 ; Fall       ; CLOCK_50        ;
;  KEY[0]   ; CLOCK_50   ; 3.848 ; 3.848 ; Fall       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------------+
; Hold Times                                                              ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; KEY[*]    ; CLOCK_50   ; -1.824 ; -1.824 ; Fall       ; CLOCK_50        ;
;  KEY[0]   ; CLOCK_50   ; -1.824 ; -1.824 ; Fall       ; CLOCK_50        ;
+-----------+------------+--------+--------+------------+-----------------+


+-----------------------------------------------------------------------+
; Clock to Output Times                                                 ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; saida[*]  ; CLOCK_50   ; 7.555 ; 7.555 ; Rise       ; CLOCK_50        ;
;  saida[0] ; CLOCK_50   ; 7.318 ; 7.318 ; Rise       ; CLOCK_50        ;
;  saida[1] ; CLOCK_50   ; 7.364 ; 7.364 ; Rise       ; CLOCK_50        ;
;  saida[2] ; CLOCK_50   ; 7.516 ; 7.516 ; Rise       ; CLOCK_50        ;
;  saida[3] ; CLOCK_50   ; 7.555 ; 7.555 ; Rise       ; CLOCK_50        ;
;  saida[4] ; CLOCK_50   ; 7.278 ; 7.278 ; Rise       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-----------------------------------------------------------------------+
; Minimum Clock to Output Times                                         ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; saida[*]  ; CLOCK_50   ; 4.084 ; 4.084 ; Rise       ; CLOCK_50        ;
;  saida[0] ; CLOCK_50   ; 4.102 ; 4.102 ; Rise       ; CLOCK_50        ;
;  saida[1] ; CLOCK_50   ; 4.119 ; 4.119 ; Rise       ; CLOCK_50        ;
;  saida[2] ; CLOCK_50   ; 4.187 ; 4.187 ; Rise       ; CLOCK_50        ;
;  saida[3] ; CLOCK_50   ; 4.200 ; 4.200 ; Rise       ; CLOCK_50        ;
;  saida[4] ; CLOCK_50   ; 4.084 ; 4.084 ; Rise       ; CLOCK_50        ;
+-----------+------------+-------+-------+------------+-----------------+


+-------------------------------------------------------------------+
; Setup Transfers                                                   ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; CLOCK_50   ; CLOCK_50 ; 1700     ; 40       ; 0        ; 2        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------+
; Hold Transfers                                                    ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; CLOCK_50   ; CLOCK_50 ; 1700     ; 40       ; 0        ; 2        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 1     ; 1    ;
; Unconstrained Input Port Paths  ; 2     ; 2    ;
; Unconstrained Output Ports      ; 5     ; 5    ;
; Unconstrained Output Port Paths ; 5     ; 5    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Warning (125092): Tcl Script File ram.qip not found
    Info (125063): set_global_assignment -name QIP_FILE ram.qip
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 12.1 Build 177 11/07/2012 SJ Web Edition
    Info: Processing started: Sun Aug 04 20:00:31 2013
Info: Command: quartus_sta top -c top
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow Model
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -5.602
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -5.602       -66.592 CLOCK_50 
Info (332146): Worst-case hold slack is 0.391
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.391         0.000 CLOCK_50 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -1.627
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.627       -94.460 CLOCK_50 
Info (332001): The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -2.549
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.549       -25.443 CLOCK_50 
Info (332146): Worst-case hold slack is 0.215
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.215         0.000 CLOCK_50 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -1.627
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.627       -94.460 CLOCK_50 
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 342 megabytes
    Info: Processing ended: Sun Aug 04 20:00:33 2013
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


