Analysis & Synthesis report for top
Sun Aug 04 20:00:13 2013
Quartus II 32-bit Version 12.1 Build 177 11/07/2012 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. State Machine - |top|EA
 10. Registers Removed During Synthesis
 11. Removed Registers Triggering Further Register Optimizations
 12. General Register Statistics
 13. Registers Added for RAM Pass-Through Logic
 14. Source assignments for RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated
 15. Parameter Settings for Inferred Entity Instance: RAM:R0|altsyncram:mem_rtl_0
 16. altsyncram Parameter Settings by Entity Instance
 17. Port Connectivity Checks: "RAM:R0"
 18. Elapsed Time Per Partition
 19. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Aug 04 20:00:13 2013    ;
; Quartus II 32-bit Version          ; 12.1 Build 177 11/07/2012 SJ Web Edition ;
; Revision Name                      ; top                                      ;
; Top-level Entity Name              ; top                                      ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 61                                       ;
;     Total combinational functions  ; 45                                       ;
;     Dedicated logic registers      ; 28                                       ;
; Total registers                    ; 28                                       ;
; Total pins                         ; 13                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 160                                      ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                      ; top                ; top                ;
; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                             ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                         ; Library ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+---------+
; top.vhd                          ; yes             ; User VHDL File               ; C:/tmp/RAM/top.vhd                                                   ;         ;
; ram.vhd                          ; yes             ; Auto-Found VHDL File         ; C:/tmp/RAM/ram.vhd                                                   ;         ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/altsyncram.tdf        ;         ;
; stratix_ram_block.inc            ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/stratix_ram_block.inc ;         ;
; lpm_mux.inc                      ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/lpm_mux.inc           ;         ;
; lpm_decode.inc                   ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/lpm_decode.inc        ;         ;
; aglobal121.inc                   ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/aglobal121.inc        ;         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/a_rdenreg.inc         ;         ;
; altrom.inc                       ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/altrom.inc            ;         ;
; altram.inc                       ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/altram.inc            ;         ;
; altdpram.inc                     ; yes             ; Megafunction                 ; c:/altera/12.1/quartus/libraries/megafunctions/altdpram.inc          ;         ;
; db/altsyncram_45c1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/tmp/RAM/db/altsyncram_45c1.tdf                                    ;         ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+---------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 61    ;
;                                             ;       ;
; Total combinational functions               ; 45    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 28    ;
;     -- 3 input functions                    ; 10    ;
;     -- <=2 input functions                  ; 7     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 41    ;
;     -- arithmetic mode                      ; 4     ;
;                                             ;       ;
; Total registers                             ; 28    ;
;     -- Dedicated logic registers            ; 28    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 13    ;
; Total memory bits                           ; 160   ;
; Embedded Multiplier 9-bit elements          ; 0     ;
; Maximum fan-out                             ; 33    ;
; Total fan-out                               ; 280   ;
; Average fan-out                             ; 3.08  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                    ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                             ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------+--------------+
; |top                                      ; 45 (36)           ; 28 (17)      ; 160         ; 0            ; 0       ; 0         ; 13   ; 0            ; |top                                                            ;              ;
;    |RAM:R0|                               ; 9 (9)             ; 11 (11)      ; 160         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|RAM:R0                                                     ;              ;
;       |altsyncram:mem_rtl_0|              ; 0 (0)             ; 0 (0)        ; 160         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|RAM:R0|altsyncram:mem_rtl_0                                ;              ;
;          |altsyncram_45c1:auto_generated| ; 0 (0)             ; 0 (0)        ; 160         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated ;              ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                          ;
+-----------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+-----------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32           ; 5            ; 32           ; 5            ; 160  ; None ;
+-----------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+


Encoding Type:  One-Hot
+-------------------------------+
; State Machine - |top|EA       ;
+-------+-------+-------+-------+
; Name  ; EA.S2 ; EA.S1 ; EA.S0 ;
+-------+-------+-------+-------+
; EA.S0 ; 0     ; 0     ; 0     ;
; EA.S1 ; 0     ; 1     ; 1     ;
; EA.S2 ; 1     ; 0     ; 1     ;
+-------+-------+-------+-------+


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; dt_in[5..7]                            ; Stuck at GND due to stuck port data_in ;
; maior[6,7]                             ; Merged with maior[5]                   ;
; maior[5]                               ; Stuck at GND due to stuck port data_in ;
; RAM:R0|mem_rtl_0_bypass[2]             ; Merged with endereco[0]                ;
; RAM:R0|mem_rtl_0_bypass[4]             ; Merged with endereco[1]                ;
; RAM:R0|mem_rtl_0_bypass[6]             ; Merged with endereco[2]                ;
; RAM:R0|mem_rtl_0_bypass[8]             ; Merged with endereco[3]                ;
; RAM:R0|mem_rtl_0_bypass[10]            ; Merged with endereco[4]                ;
; EA.S0                                  ; Lost fanout                            ;
; Total Number of Removed Registers = 12 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                        ;
+---------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal        ; Registers Removed due to This Register ;
+---------------+---------------------------+----------------------------------------+
; dt_in[6]      ; Stuck at GND              ; maior[5]                               ;
;               ; due to stuck port data_in ;                                        ;
+---------------+---------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 28    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------+
; Registers Added for RAM Pass-Through Logic     ;
+-----------------------------+------------------+
; Register Name               ; RAM Name         ;
+-----------------------------+------------------+
; RAM:R0|mem_rtl_0_bypass[0]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[1]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[2]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[3]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[4]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[5]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[6]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[7]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[8]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[9]  ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[10] ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[11] ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[12] ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[13] ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[14] ; RAM:R0|mem_rtl_0 ;
; RAM:R0|mem_rtl_0_bypass[15] ; RAM:R0|mem_rtl_0 ;
+-----------------------------+------------------+


+-----------------------------------------------------------------------------------+
; Source assignments for RAM:R0|altsyncram:mem_rtl_0|altsyncram_45c1:auto_generated ;
+---------------------------------+--------------------+------+---------------------+
; Assignment                      ; Value              ; From ; To                  ;
+---------------------------------+--------------------+------+---------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                   ;
+---------------------------------+--------------------+------+---------------------+


+------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: RAM:R0|altsyncram:mem_rtl_0 ;
+------------------------------------+----------------------+------------------+
; Parameter Name                     ; Value                ; Type             ;
+------------------------------------+----------------------+------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped          ;
; WIDTH_A                            ; 5                    ; Untyped          ;
; WIDTHAD_A                          ; 5                    ; Untyped          ;
; NUMWORDS_A                         ; 32                   ; Untyped          ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped          ;
; WIDTH_B                            ; 5                    ; Untyped          ;
; WIDTHAD_B                          ; 5                    ; Untyped          ;
; NUMWORDS_B                         ; 32                   ; Untyped          ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped          ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped          ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped          ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped          ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped          ;
; BYTE_SIZE                          ; 8                    ; Untyped          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped          ;
; INIT_FILE                          ; UNUSED               ; Untyped          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped          ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped          ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped          ;
; ENABLE_ECC                         ; FALSE                ; Untyped          ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped          ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped          ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped          ;
; CBXI_PARAMETER                     ; altsyncram_45c1      ; Untyped          ;
+------------------------------------+----------------------+------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                        ;
+-------------------------------------------+-----------------------------+
; Name                                      ; Value                       ;
+-------------------------------------------+-----------------------------+
; Number of entity instances                ; 1                           ;
; Entity Instance                           ; RAM:R0|altsyncram:mem_rtl_0 ;
;     -- OPERATION_MODE                     ; DUAL_PORT                   ;
;     -- WIDTH_A                            ; 5                           ;
;     -- NUMWORDS_A                         ; 32                          ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                ;
;     -- WIDTH_B                            ; 5                           ;
;     -- NUMWORDS_B                         ; 32                          ;
;     -- ADDRESS_REG_B                      ; CLOCK0                      ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                        ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                   ;
+-------------------------------------------+-----------------------------+


+----------------------------------------+
; Port Connectivity Checks: "RAM:R0"     ;
+------+-------+----------+--------------+
; Port ; Type  ; Severity ; Details      ;
+------+-------+----------+--------------+
; en   ; Input ; Info     ; Stuck at VCC ;
+------+-------+----------+--------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:01     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 12.1 Build 177 11/07/2012 SJ Web Edition
    Info: Processing started: Sun Aug 04 20:00:10 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Warning (125092): Tcl Script File ram.qip not found
    Info (125063): set_global_assignment -name QIP_FILE ram.qip
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (12021): Found 2 design units, including 1 entities, in source file top.vhd
    Info (12022): Found design unit 1: top-top_beh
    Info (12023): Found entity 1: top
Warning (12019): Can't analyze file -- file rom.vhd is missing
Info (12127): Elaborating entity "top" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at top.vhd(65): signal "dt_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (12125): Using design file ram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: RAM-bhv
    Info (12023): Found entity 1: RAM
Info (12128): Elaborating entity "RAM" for hierarchy "RAM:R0"
Warning (276020): Inferred RAM node "RAM:R0|mem_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Info (19000): Inferred 1 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "RAM:R0|mem_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 5
        Info (286033): Parameter WIDTHAD_A set to 5
        Info (286033): Parameter NUMWORDS_A set to 32
        Info (286033): Parameter WIDTH_B set to 5
        Info (286033): Parameter WIDTHAD_B set to 5
        Info (286033): Parameter NUMWORDS_B set to 32
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (12130): Elaborated megafunction instantiation "RAM:R0|altsyncram:mem_rtl_0"
Info (12133): Instantiated megafunction "RAM:R0|altsyncram:mem_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info (12134): Parameter "WIDTH_A" = "5"
    Info (12134): Parameter "WIDTHAD_A" = "5"
    Info (12134): Parameter "NUMWORDS_A" = "32"
    Info (12134): Parameter "WIDTH_B" = "5"
    Info (12134): Parameter "WIDTHAD_B" = "5"
    Info (12134): Parameter "NUMWORDS_B" = "32"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_45c1.tdf
    Info (12023): Found entity 1: altsyncram_45c1
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "saida[5]" is stuck at GND
    Warning (13410): Pin "saida[6]" is stuck at GND
    Warning (13410): Pin "saida[7]" is stuck at GND
Info (17049): 1 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 3 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "KEY[1]"
    Warning (15610): No output dependent on input pin "KEY[2]"
    Warning (15610): No output dependent on input pin "KEY[3]"
Info (21057): Implemented 84 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 5 input pins
    Info (21059): Implemented 8 output pins
    Info (21061): Implemented 66 logic cells
    Info (21064): Implemented 5 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings
    Info: Peak virtual memory: 388 megabytes
    Info: Processing ended: Sun Aug 04 20:00:13 2013
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:03


