System Reliability – 34653-02

“Test of Digital Systems”

Fall 2008/2

Catholic University of RS (PUCRS), Informatics Faculty/PPGCC

Prof. Eduardo Bezerra

Term project definition: design and implementation of a testing process for a RISC microprocessor core.

• Design activities

  • Target processor selection (suggestion: Plasma processor).

  • Definition and selection of an abstract execution graph for each instruction of the microprocessor under test.

  • Definition and selection of a minimun instruction set for the test, using the structural method for graph analysis shown in class (.doc or .pdf).

  • Definition and selection of a minimun instruction set needed to increase the test coverage, using the functional method for graph analysis shown in class (.doc or .pdf).

  • Define the minimun instrucion set and the sequence of instructions (assembly program) to be used for performing the microprocessor's testing.

  • Technical report writing up (to be added to the paper).

• Implementation activities

  • Define a case study architecture, and implement a couple of simple applications to run on this platform. Download and test everything using an SRAM based FPGA

  • Test management: definition of a strategy for performing a microprocessors' self-test in a periodic way. Define the mechanism for triggering the testing processes.

  • Define a strategy for fault injection and for the test execution. For instance, perform the download of a faulty microprocessor between two testing executions.

• Writing up activities

  • Technical report writing up (to be added to the paper).

• Useful tips

  • Test procedure for a simpler microprocessor core: TESDI.

  • Paper describing another approach for the software-based test of a RISC (Plasma) processor: Low-Cost Software-Based Self-Testing of RISC Processor Cores, N. Kranitis et. al., DATE'03, IEEE Computer Society, 2003.

  • Paper template: LATW2008.